JP5320275B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

The present invention relates to a method of manufacturing a semi-conductor device and its.

  Developments related to high-density mounting technology for semiconductor devices are in progress in response to the needs for higher performance and smaller size of portable information devices, small electronic devices, and the like. Among high-density packaging technologies, a wafer level package (WLP) technology for processing a semiconductor wafer having a semiconductor integrated circuit in the form of a wafer, and a chip size package (for each semiconductor chip package) CSP) technology is widely used.

  FIG. 1 is a diagram illustrating a conventional semiconductor wafer and a wafer level package.

(Wafer level package (WLP))
FIG. 1A illustrates a plan view of a semiconductor wafer 11 having a semiconductor integrated circuit. The diameter of the semiconductor wafer 11 is referred to as an inch value, and 6, 8 and 12 inches are used in the field of high-density mounting technology. The wafer level package (WLP) packaging technique is a technique for collectively packaging the entire semiconductor wafer 11 in which individual semiconductor chips 13 are assembled, such as rewiring and resin sealing. In the final packaging process, the semiconductor chip package is obtained by cutting and dividing at the scribe line 12. Each package has an outer dimension equal to or slightly larger than the size of the semiconductor chip, and is therefore referred to as a chip size package (CSP).

  FIG. 1B illustrates a state in which the semiconductor wafer 11 is packaged by WLP packaging, and the WLP package at a position corresponding to the cutting line XX of the semiconductor wafer 11 in FIG. FIG. In FIG. 2B, the semiconductor chip 13 has a semiconductor integrated circuit 14, an electrode pad 15, and a protective film 16, and is provided adjacent to the same semiconductor wafer 11. A rewiring layer 111 is formed on the semiconductor wafer 11. The rewiring layer 111 includes an internal connection terminal 17, a first insulating layer 18, a second insulating layer 19, a wiring 20, an external connection terminal 21, a solder resist layer 22, and the like. The rewiring layer 111 is formed by package processing such as wire bonding, insulating layer lamination, and wiring plating. Each semiconductor chip packaged in this way is separated from an adjacent semiconductor chip by a scribe line 42 at the substrate cutting position C. The term “semiconductor wafer” is mainly used to mean “semiconductor substrate in the shape of a wafer”.

(Scribe area)
FIG. 2 is a diagram illustrating a region of a semiconductor wafer. FIG. 1A is a plan view of a semiconductor wafer 11 having a semiconductor integrated circuit, and FIG. 2B is an enlarged view of a cross section of the semiconductor wafer 11 taken along a cutting line XX in FIG. A region S of the semiconductor integrated circuit indicates a region where the semiconductor integrated circuit 14 is provided. A region R disposed between the regions S of the semiconductor integrated circuit is a scribe region. The substrate cutting position C located near the center in the width direction of the scribe region R is a position reference for a dicer device or the like for cutting each semiconductor chip 13 into pieces. The scribe line 12 indicates a cutting margin and corresponds to a blade thickness (not shown) of the dicer device.

(Chip size package (CSP) having two insulating layers having different elastic moduli)
FIG. 3 is a diagram illustrating a conventional CSP. FIG. 1A shows a CSP having two insulating layers. A technique is disclosed in which two insulating layers 18 and 19 having different elastic moduli are provided on the semiconductor chip 13 to suppress the occurrence of warping due to shrinkage after thermosetting. For example, the elastic modulus of the low-elasticity first insulating layer 18 is 20 MPa or more and less than 1000 MPa, and the elastic modulus of the high-elasticity second insulating layer 19 is 1000 MPa or more (Patent Document 1).

  FIG. 3B is a diagram illustrating another conventional CSP. The semiconductor element (semiconductor chip) 31 includes an insulating layer 32 a formed on the main surface 32, an insulating layer 33 a formed on the side surface 33 that defines the outer edge of the main surface 32, and a back surface 34 that faces the main surface 32. The formed insulating layer 34a and the like are provided. Since the insulating layer is formed on the side surface of the semiconductor element, physical impact can be reduced to protect the side surface of the semiconductor element, and chipping can be prevented (Patent Document 2).

JP 2008-311593 A JP 2001-168231 A

  FIG. 3C is a diagram illustrating a state of occurrence of cracks in the internal connection terminals in the package in a conventional CSP having two insulating layers. The crack is generated from the boundary surface 23 between the two insulating layers 18 and 19 of the internal connection terminal 17 that connects the electrode pad 15 provided on the semiconductor chip 13 and the wiring 20. A shearing force may be generated at the boundary surface 23 between the two layers due to a difference in thermal expansion between the two insulating layers 18 and 19, and a crack may be generated at the internal connection terminal 17 existing at the boundary portion of the insulating layer.

The present invention has been made in view of the problems described above, it does not cause cracks in the internal connection terminals, and an object thereof is to provide a method of manufacturing a semiconductor device and its having improved reliability.

The semiconductor device is provided so as to expose a semiconductor integrated circuit formed on one surface side of a semiconductor substrate, an electrode pad provided on the semiconductor integrated circuit, and the electrode pad on the semiconductor integrated circuit. A semiconductor chip having a protective film; an internal connection terminal formed on the electrode pad; a notch formed on an edge of the semiconductor chip; and a first part formed so as to fill the notch A first insulating layer, a side surface of the internal connection terminal, a second insulating layer formed to cover the first insulating layer and the protective film, and the first insulating layer has the notch It is formed only to the formation region to have requirements Rukoto.
In addition, a manufacturing method of the present semiconductor device prepares a semiconductor substrate including a plurality of semiconductor chips having electrode pads formed on a semiconductor integrated circuit and a scribe region disposed between each of the plurality of semiconductor chips. Corresponding to the opening of the protective mask, and a step of forming a protective mask having an opening that covers the semiconductor integrated circuit and the electrode pad and exposes the scribe region on the semiconductor substrate. A step of processing a groove portion in the scribe region, a step of forming a first insulating layer filling the groove portion using the protective mask as a screen mask, and removing the protective mask on the electrode pad. Forming an internal connection terminal on the first insulating layer; forming a second insulating layer on the first insulating layer and the semiconductor substrate; and forming a wiring layer on the second insulating layer. And that steps may be a requirement that has a.

Does not cause cracks in the internal connection terminals, it is possible to provide a method of manufacturing a semiconductor device and its having improved reliability.

It is a figure which illustrates the conventional semiconductor wafer and a wafer level package. It is a figure which illustrates the field of the conventional semiconductor wafer. It is a figure which illustrates the conventional chip size package. 1 is a diagram illustrating a semiconductor device according to a first embodiment of the invention. It is a figure which illustrates the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a figure which illustrates the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a figure which illustrates the form of the typical semiconductor device in the process of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a figure which illustrates the form of the typical semiconductor device in the process of the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention. It is a figure which illustrates the cross section of CSP which concerns on the 2nd Embodiment of this invention.

  The best mode for carrying out the present invention will be described below with reference to the drawings. In the description of each drawing, the same components and the like that are common to each drawing are denoted by the same reference numerals, and the description thereof may be omitted when overlapping.

<First Embodiment>
The invention according to the first embodiment of the present invention is an invention of a method for manufacturing a semiconductor device relating to the use of a protective mask. For the description of the present manufacturing method, the outline of the invention as a premise thereof will be described below.

<Invention that is the premise of the invention according to the first embodiment>
FIG. 4A is a diagram illustrating a CSP package having a structure in which the internal connection terminals 47 are substantially covered only by the second insulating layer 49. Since the side surface of the internal connection terminal 47 is covered only by the second insulating layer 49, the influence of the shearing force and the like applied when the internal connection terminal is covered by the two insulating layers should be avoided. Can do. Further, a first insulating layer 48 is provided in the groove M formed at the edge of the semiconductor integrated circuit 44 of the semiconductor chip 43, and two insulating layers 48 and 49 are provided above the surface of the groove M, thereby providing a semiconductor. The adhesion strength between the chip and the insulating layer is increased. The adhesion strength is increased by the adhesion between the roughened surface of the groove M and the first insulating layer and the two-layer configuration of the first insulating layer and the second insulating layer held by the groove shape. ing.

  FIG. 4B is a diagram showing a method of manufacturing a CSP package in which the internal connection terminals are covered with almost one insulating layer. The manufacturing process includes a protective mask attaching step (S1001), a groove processing step (S1002), a protective mask removing step (S1003), a screen mask arranging step (S1004), a first insulating layer forming step (S1005), and an internal connection terminal formation. A step (S1006), a second insulating layer forming step (S1007), a wiring layer forming step (S1008), an external connection terminal forming step (S1009), and a CSP singulation step (S1010). Among these, an outline is demonstrated about the process (S1001-S1005) regarding a protective mask and a screen mask.

(S1001. Protective mask pasting)
This is a step of attaching a protective mask used for processing the groove M (FIG. 4A). The groove part M is formed by a processing method such as wet blasting in the groove part processing step (S1002). The surface of the groove part M is in a roughened state having fine irregularities. In the groove processing step (S1002), the protective mask has an opening having a size corresponding to the size of the groove, and protects a region around the groove M, such as a region of the semiconductor integrated circuit 44 and a part of the electrode pad 45. Used for the purpose.

(S1003. Removal of protective mask)
The protective mask is removed to secure a space for the screen mask for forming the first insulating layer.

(S1004. Screen mask arrangement)
A screen mask for forming the first insulating layer is disposed. Since WLP is processed with fine dimensions, care must be taken to ensure the positional accuracy of the arrangement.

(S1005. Formation of first insulating layer covering groove)
A paste-like first insulating layer 48 is formed in the groove M using the screen mask disposed in S1004.

  The steps after the internal connection terminal forming step (S1006) are steps such as forming a rewiring layer of the WLP package. Since the process of forming the rewiring layer will be described later, the description thereof is omitted. The present invention is an invention obtained by improving the above-mentioned invention.

  The present invention will be described below.

  FIG. 4C is a diagram illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention. The manufacturing method includes a protective mask attaching step (S101), a groove processing step (S102), a first insulating layer forming step (S103), an internal connection terminal forming step (S104), a second insulating layer forming step (S105), and a wiring layer. It has a forming step (S106), an external connection terminal forming step (S107), and a CSP separation step (S108).

  5A and 5B are diagrams illustrating exemplary semiconductor device configurations in the manufacturing method of FIG. 4C.

  Hereinafter, a method for manufacturing a semiconductor device will be described step by step with reference to the form of the semiconductor device in FIGS. 5A and 5B.

(S101. Protective mask pasting step)
The protective mask pasting step of S101 in FIG. 4C is a step of pasting a protective mask used for groove processing. The protective mask has an opening having a size corresponding to the size of the groove to be processed by the groove, and is used for the purpose of protecting the area around the groove.

  FIG. 5A shows a state in which a protective mask 53 a is stuck on the semiconductor chip 52 in the semiconductor wafer 51. The protective mask 53a is a mask having an opening 53c for protecting the region S of the semiconductor integrated circuit and forming a groove 57 (broken line display portion) in a part of the scribe region R. As the groove processing, wet blast processing, etching processing, or the like is performed on the opening 53c.

  As a material of the protective mask 53a, for example, a photosensitive dry film resist or a liquid resist can be used. The opening 53c is processed by a known exposure / development / peeling processing procedure for the resist material. In the present invention, since the protective mask 53a used in the groove processing step is continuously used in the first insulating layer forming step (S103) of the next step, the thickness change in the groove processing step is expected. The thickness T1 is calculated in advance. The change in the thickness of the protective mask 53a refers to a change in which the protective mask 53a itself is affected by wet blasting or the like at the time of groove processing, and is simultaneously worn and thinned. The thickness of the protective mask 53a can be appropriately set according to the design conditions such as the material of the protective mask, the physical properties of the semiconductor chip, the dimensions of the insulating layer, the processing conditions for the groove processing, and the like.

(S102. Groove processing)
The groove processing step of S102 in FIG. 4C is a process of forming the groove 57 (broken line display portion) around the substrate cutting position C (FIG. 5A (a)) in the scribe region R, and uses the protective mask 53a. The groove has a semicircular cross-sectional shape so that the resin of the first insulating layer can be securely bonded to the groove surface and a sufficient amount of resin of the first insulating layer can be secured. Or it is desirable to have a U-shape. About the surface layer surface of a groove part, it is desirable that it is the surface roughened state which has fine unevenness | corrugation. This is because a reliable tight bond having an anchor effect is caused between the surface layer of the roughened surface and the resin of the insulating layer. When the groove is formed by wet blasting, etching, plasma ashing, or the like, the surface of the groove can be roughened. As shown in FIG. 5B (h) which will be described later, the formed groove portion 57 has a first insulating layer 58 at the edge portion around the scribe line 12 of the packaged and separated semiconductor chip 52. It becomes a missing part.

(Wet blasting)
When wet blasting is performed as the groove processing, a slurry suspension aqueous solution containing, for example, alumina abrasive grains having a particle diameter of 10 μm to 20 μm or spherical silica abrasive grains is used as an abrasive. The concentration of the slurry aqueous solution is 14 wt%. Using a wet blasting device, a slurry suspension aqueous solution is jetted perpendicularly to the surface of the object to be processed from a nozzle placed at a distance of 10 mm from the object to be processed. The injection pressure is, for example, 0.25 MPa. In the wet blasting process, the surface of the groove can have fine irregularities by polishing the abrasive. Therefore, the tight bond with the first insulating layer adhered on the groove surface can be a strong bond with an anchor effect.

  FIG. 5A (b) is a diagram showing a state in which the groove processing is completed. The protective mask 53a is worn away to become a protective mask 53b. A groove 57 is formed in the scribe region R corresponding to the opening 53c of the protective mask 53b. The shape of the groove part 57 is semicircular or U-shaped. The protective mask 53b is worn under the influence of the groove processing, for example, wet blast processing, and the thickness is reduced from the initial T1 where it is pasted to T2 in FIG. This thickness T2 corresponds to the screen thickness in the printing application of the first insulating layer in the next step, and the thickness at the time of printing of the first insulating layer is determined. The thickness of T2 is, for example, 5 to 10 μm.

(S103. First Insulating Layer Forming Step)
FIG. 5A (c) shows a state in which the first insulating layer 58 is formed. The protective mask 53a used in the groove processing step (S102) is used as the screen mask 53b in the first insulating layer forming step (S103). The first insulating layer 58 is formed so as to cover the groove 57 having the substrate cutting position C as a substantially central position. Since the protective mask 53a is continuously used as the screen mask 53b for forming the first insulating layer, the process of removing the protective mask after the groove processing and the process of pasting, exposing, developing, and peeling the new screen mask are performed. It can be omitted.

  For the first insulating layer, an insulating resin having low elastic properties is used. The reason why low physical properties are used is to suppress the occurrence of peeling due to the difference in thermal expansion between the semiconductor chip inside the package and the insulating layer. Specifically, the value of the elastic modulus is desirably 20 MPa to 100 MPa. This desirable value range is based on the result of the following reliability confirmation test. That is, in a reliability test using a sample in which a CSP created by the manufacturing method of the present invention is mounted on a CSP mounting substrate via a metal bump, when the elastic modulus value is 20 MPa to 100 MPa, This is because the adhesiveness with the insulating layer was kept good.

  As the material of the first insulating layer, for example, a paste-like insulating resin (Non Conductive Paste, abbreviated as NCP), a paste-like anisotropic conductive resin (Anisotropic Conductive Paste, abbreviated as ACP), or the like is used. In addition, when the first insulating layer 58 is in the vicinity of the semiconductor integrated circuit 54, α-rays can be blocked by using a resin containing a polyimide compound such as polyimide or modified polyimide. Thus, malfunction in the semiconductor integrated circuit can be prevented. Furthermore, using resin containing well-known carbon black and black organic pigments, etc., cut off visible light and ultraviolet rays, and use resin containing titanium oxide etc. to block light in a wide wavelength range. Thus, malfunction in the semiconductor integrated circuit can be prevented.

  The curing conditions for forming the resin of the first insulating layer 58 can be set to a time of 60 minutes to 120 minutes in, for example, a curing furnace having an air or nitrogen atmosphere at a temperature of 175 to 185 ° C.

  The dimensions of the first insulating layer 58 are, for example, a groove width w of 40 μm to 80 μm and a thickness d of 15 μm to 20 μm in FIG. When the package is singulated as a CSP, the first insulating layer is formed with a width of approximately 20 μm to 40 μm on the four edges of the CSP.

(S104. Internal connection terminal forming step)
FIG. 5A shows a state in which the internal connection terminal 59 is connected to the electrode pad 55. The electrode pad 55 is exposed on the surface of the semiconductor wafer 51 by peeling off the protective mask (53b in FIG. 5C). Specifically, as the internal connection terminal 59, metal such as gold, copper, or aluminum is used, and metal bumps are formed by using a wire bonder device or the like using a wire of these metals as a material. Further, a ball-shaped bump may be stacked and fixed on the electrode pad 55 by using a ball bump loading device or the like. The internal connection terminal can be formed by plating. In particular, when the pitch between adjacent electrode pads and wiring is fine, it is effective to form internal connection terminals by plating.

(S105. Second Insulating Layer Forming Step)
FIG. 5B (e) shows a state in which the second insulating layer 61 is formed on the surface 60 formed by the semiconductor integrated circuit 54. Here, the surface 60 formed by the semiconductor integrated circuit 54 indicates the surface of the semiconductor wafer 51 on the side where the semiconductor integrated circuit 54 is formed. The second insulating layer 61 covers the entire surface 60, that is, the entire region S and scribe region R of the semiconductor integrated circuit. The region S of the semiconductor integrated circuit has an internal connection terminal 59, an electrode pad 55, and a protective film 56, and the scribe region R located between the regions S of the semiconductor integrated circuit includes the first insulating layer 58 and other parts. The semiconductor wafer has a portion R0, and the second insulating layer 61 covers the entire regions S and R.

  The second insulating layer 61 uses an insulating resin having higher elastic properties than the first insulating layer 58. For example, a material having an elastic modulus value exceeding 100 MPa is used. The elastic modulus can be selected as appropriate according to the physical properties and dimensions of the semiconductor chip, the characteristics of the mounting substrate on which the CSP is to be mounted, the use conditions, and the like. As a material of the second insulating layer 61, for example, a film-like insulating resin (Non Conductive Film, abbreviated as NCF) is used. Further, not only NCF but also a filler-containing epoxy resin used for the insulating layer of the build-up substrate can be laminated. The thickness of the second insulating layer is, for example, 30 μm to 40 μm.

(Planarization of the second insulating layer)
In order to ensure the flatness of the surface layer of the second insulating layer 61 as the surface supporting the wiring constituting the rewiring layer, the surface layer is flattened. Further, the top portion 59 a of the internal connection terminal 59 is exposed on the surface layer of the second insulating layer 61 for connection between the internal connection terminal 59 and the wiring. A well-known method can be used for planarizing the surface layer and exposing the top of the internal connection terminal. For example, the second insulating layer 61 is heated to soften, and a rigid body having a flat surface is pressed from the surface layer side of the second insulating layer 61 toward the semiconductor integrated circuit 54 side. A method of vibrating in the direction of the surface to expose the tops of the internal connection terminals, a method of grinding the surface layer of the second insulating layer 61 with a grinding apparatus equipped with a grinding roll or the like can be used. Further, the top portion 59 a of the internal connection terminal 59 can be exposed by performing plasma ashing or the like on the surface layer of the second insulating layer 61.

(S106. Wiring layer forming step)
FIG. 5B shows a state in which the seed layer 62 and the photoresist layer 63 for forming the wiring layer are formed on the second insulating layer 61. A well-known electrolytic plating method can be used for forming the wiring layer. That is, a seed layer 62 for electrolytic plating is formed using a sputtering apparatus or the like, a photoresist layer 63 is laminated, and after curing, a space in which wiring is to be formed is provided by exposure, development, and peeling processes. Next, wiring is formed by filling the space by electrolytic plating.

  (G) of FIG. 5B has shown the state by which the wiring 64 was formed by electrolytic plating. Copper or the like is used as the wiring material. A nickel layer is formed on the surface of the wiring 64 to which the external connection terminal is connected in order to improve adhesion, and a palladium layer is further formed on the connection surface with the external connection terminal in order to improve conductivity. A layer can be formed. Further, the gold layer can be formed directly on the nickel layer according to the design conditions.

(S107. External connection terminal forming step)
FIG. 5B (h) shows a state in which a solder resist layer 66 is provided on the wiring 64 and the second insulating layer 61 and the external connection terminal 65 is connected. The external connection terminal 65 may be made of a material such as a metal ball using a solder such as tin, silver, or copper, or a solder ball having copper as a core. Through the external connection terminal 65, the separated CSP is mounted on a wiring board or the like used for an electronic application device or the like. When an external connection terminal such as a solder ball is already formed on the side of the wiring board on which the CSP is to be mounted, the rewiring layer 151 is provided with a land connected to the wiring as a connection part on the CSP side. The solder resist layer 66 shown in FIG.

(S108. CSP singulation process)
In this process, individual CSPs are formed from WLP formed by packaging a rewiring layer on a semiconductor wafer. In FIG. 5B (h), a plurality of semiconductor chips 52 are connected in a semiconductor wafer 51, a rewiring layer 151 is formed on the surface of the semiconductor wafer 51 on the side of the semiconductor integrated circuit 54, and a wafer level package (WLP) is formed. It has a form. The WLP is separated into individual CSPs by the scribe line 12 having the substrate cutting position C as the center line. Cutting and separation into individual pieces are performed using a dicing saw device, a laser processing device, or the like.

  The dimension of the plane of the CSP is, for example, 7 mm × 7 mm, 10 mm × 14 mm, or the like. The thickness of the CSP is 400 μm to 600 μm including the external connection terminals, for example. The thickness when the external connection terminal is not connected is, for example, 200 μm to 400 μm. In addition, the dimension of CSP can be suitably determined according to the use conditions of a semiconductor device and an electronic application apparatus.

  The semiconductor device manufacturing method according to the first embodiment of the present invention can be provided by the above steps S101 to S107.

<Temperature cycle test results>
The test results of the reliability of the internal connection terminals of the semiconductor device formed on the basis of the manufacturing method shown in the first embodiment are as follows.

  Each CSP separated by cutting at the substrate cutting position C in (h) of FIG. 5B is mounted TC test, that is, mounted on a wiring board and subjected to a temperature cycle test, and an internal connection terminal (gold bump) of the CSP. ) Was observed for cracks. The CSP is mounted on a wiring board (not shown) by forming a solder bump made of a material such as silver or copper as the external connection terminal 65, and connecting it to the connection terminal on the wiring board made of an epoxy resin or the like. After connection by reflow, the solder bump and the surface of the CSP solder resist layer 66 were sealed with an underfill material. As a sample to be compared in the reliability test, the CSP separated in the scribe line 12 shown in FIG. 1B, which is characterized by two insulating layers, is mounted on a wiring board, and "Sample 1" Used as. In the CSP of Sample 1, the internal connection terminal 17 is located at a position penetrating the boundary surface 23 of the two insulating layers 18 and 19 and is covered with the two insulating layers 18 and 19. Comparison was made between the sample “sample 2” and the sample 1 in which the internal connection terminal portion of the present invention is covered only with one insulating layer resin. The environmental conditions of the temperature cycle test were 1000 cycles of the temperature cycle condition of immersing in an atmosphere having a maximum temperature of 125 ° C. and a minimum temperature of −40 ° C. every 9 minutes, and then measuring electrical characteristics and observing a cross section. The CSP used for the test is a package having a size of 10 mm × 14 mm, the number of packages of “Sample 1” and “Sample 2” is 10 and the occurrence rate of cracks is 10/10 and 0 / respectively. 10. This test result shows that the CSP having the first insulating layer in the notched portion with the roughened surface according to the present invention has an effect of suppressing the occurrence of cracks in the internal connection terminal. .

<Effect of the first embodiment>
A package with improved reliability by covering the vicinity of the internal connection terminal of the CSP package with only one type of insulating layer and forming the edge of the semiconductor integrated circuit with two types of insulating layers, thereby preventing the internal connection terminal from cracking. The manufacturing method of can be provided.

  Regarding the manufacturing method, further, the protective mask used in the groove processing step is continuously used as a screen mask for forming the first insulating layer in the first insulating layer forming step, thereby simplifying the production process and reducing the production cost. Can be achieved.

<Modification of First Embodiment>
The groove provided in the scribe region can be processed by etching without using wet blasting. As a solution used for etching, for example, a solution obtained by adding isopropyl alcohol to 4-methyl ammonium hydroxide (TMAH), hydrofluoric acid (HF), or potassium hydroxide (KOH) solution can be used. In addition, since a fine uneven shape can be formed on the groove surface by etching, the tight bonding between the first insulating layer and the groove surface to be bonded on the groove surface is strong with a remarkable anchor effect. It can be a bond.

<Effects of Modification of First Embodiment>
By continuously using the protective mask used for the etching process in the groove processing step as a screen mask for forming the first insulating layer in the first insulating layer forming step, the production process is simplified and the production cost is reduced. Can be planned.

<Second Embodiment>
FIG. 6 is a diagram illustrating a cross section of a CSP according to the second embodiment of the invention. The CSP is mounted on an external wiring board 70 via an external connection terminal 65. Even when the internal connection terminals are not only 68 around the area S of the semiconductor integrated circuit but also 69 inside the area S, the occurrence of cracks in the internal connection terminals can be avoided. The semiconductor chip 130 has two insulating layers of a first insulating layer 58 and a second insulating layer 61 only at the edge 67. In the case of a specific condition, that is, when the design conditions such as the dimensions of the semiconductor chip 130 and the heat generation characteristics of the semiconductor integrated circuit 54 are specific, in the CSP having the structure of the two insulating layers only at the edge 67 portion, Generation of internal peeling and deformation due to the influence of thermal stress and the like can be avoided. As shown in FIG. 6, even when the internal connection terminal 69 exists inside the region S of the semiconductor integrated circuit, the insulating layer covering the internal connection terminal 69 is only the second insulating layer 61. Thus, the internal connection terminal 69 does not crack due to the difference in shear stress between two different insulating layers.

<Effects of Second Embodiment>
Even when the internal connection terminal exists inside the region of the surface of the semiconductor integrated circuit, since it does not receive the shearing force at the boundary portion of the two insulating layers at the time of thermal expansion or the like, Generation of cracks at the boundary portion of the insulating layer can be avoided. Therefore, the reliability of the internal connection terminals in the package can be improved.

<Third Embodiment>
The resin material used for the insulating layer contains an inorganic filler (filler), and the inorganic filler may contain a small amount of uranium or thorium. Since α rays emitted from these elements and the like may cause a soft error in the operation of the semiconductor integrated circuit, the resin material of the insulating layer adjacent to the semiconductor integrated circuit has an α ray shielding function. The occurrence of soft errors can be avoided by including polyimide or a polyimide compound.

  In the CSP having the configuration illustrated in FIG. 5B (h), the portion of the semiconductor integrated circuit 54 that is covered with the second insulating layer 61 and covered with the first insulating layer 58 is the substrate cutting position C on the edge. It is limited to the groove processed in the vicinity. Therefore, in the second insulating layer 61, it is desirable to set the total content of polyimide, polyimide compound, or the like more so that the α-ray shielding has a stronger function than the first insulating layer. .

<Effect of the third embodiment>
By using a material having a strong α-ray shielding function as the resin material of the insulating layer covering the region of the semiconductor integrated circuit, it is possible to effectively avoid the occurrence of a soft error in the semiconductor integrated circuit.

<Other Embodiments According to the Present Invention>
The preferred embodiment according to the present invention has been described in detail above. However, the present invention is not limited to the above-described embodiment, and various modifications can be made to the above-described embodiment without departing from the scope of the present invention. Variations and substitutions can be added.

  For example, in the groove processing step, a method for manufacturing a groove surface by using a dicing saw apparatus and plasma ashing is possible. In the above <First Embodiment> and <Modified Example of the First Embodiment>, wet blasting and etching solution are used for groove processing, respectively, but dicing with a blade having a groove shape mounted. Using a saw device, the semiconductor wafer is processed into a half-cut shape to form only the groove shape, and then the surface of the processed groove is subjected to plasma ashing or the like to seal the surface of the groove and the insulating layer The adhesive force with the resin can be improved. The plasma ashing process activates the surface of the groove by using a plasma ashing device to scatter and clean organic contaminants on the surface of the groove with a gas such as oxygenated oxygen or nitrogen. is there. Accordingly, the adhesion between the groove surface and the sealing resin of the insulating layer is improved, and the internal insulating layer is prevented from being peeled off against the occurrence of internal stress caused by thermal expansion. The form can be maintained. As described above, it is possible to provide a method for manufacturing a package with improved reliability.

11, 51 Semiconductor wafer 12 Scribe lines 13, 52, 130 Semiconductor chips 14, 54 Semiconductor integrated circuits 15, 55 Electrode pads 16, 56 Protective films 17, 47, 59, 68, 69 Internal connection terminals 18, 58 First insulating layer 19, 61 Second insulating layer 20, 64 Wiring 21, 65 External connection terminal 22, 66 Solder resist layer 53a Protection mask 53b Screen mask (protection mask)
53c Opening 57 of protective mask 53a Groove 59a Top 60 of internal connection terminal 59 Surface 62 formed by semiconductor integrated circuit 54 Seed layer 63 Photoresist layer 67 Edge 70 of semiconductor chip 130 Wiring substrate 111, 151 Rewiring layer C Substrate cutting Position d Thickness R of first insulating layer 58 Scribe region R0 Other semiconductor wafer portion S Semiconductor integrated circuit region T1 Protective mask 53a thickness T2 Protective mask 53b thickness w Groove width

Claims (10)

A semiconductor integrated circuit formed on one surface side of the semiconductor substrate; an electrode pad provided on the semiconductor integrated circuit; and a protective film provided on the semiconductor integrated circuit so as to expose the electrode pad. A semiconductor chip,
  Internal connection terminals formed on the electrode pads;
  A notch formed in an edge of the semiconductor chip;
  A first insulating layer formed to fill the notch,
  A side surface of the internal connection terminal, the first insulating layer, and a second insulating layer formed to cover the protective film,
  The first insulating layer is a semiconductor device formed only in a region where the notch is formed. 2. The semiconductor device according to claim 1, wherein the first insulating layer is formed only in a region where the notch is formed, over the notch and a part of the second insulating layer. The semiconductor device according to claim 1, wherein a surface of the notch is a roughened surface. The semiconductor device according to claim 1, wherein the second insulating layer uses an insulating resin having a higher elastic modulus than the first insulating layer. 4. The semiconductor device according to claim 1, wherein the second insulating layer has a higher content of polyimide or a polyimide compound than the first insulating layer. 5. Preparing a semiconductor substrate comprising a plurality of semiconductor chips having electrode pads formed on a semiconductor integrated circuit, and a scribe region disposed between each of the plurality of semiconductor chips;
Forming a protective mask on the semiconductor substrate having an opening that covers the semiconductor integrated circuit and the electrode pad region and exposes the scribe region;
A step of processing a groove in the scribe region corresponding to the opening of the protective mask;
Using the protective mask as a screen mask to form a first insulating layer filling the groove;
Removing the protective mask and forming an internal connection terminal on the electrode pad;
Forming a second insulating layer on the first insulating layer and the semiconductor substrate;
The method of manufacturing a semiconductor device that Yusuke and step, of forming a wiring layer on the second insulating layer. Method for producing a as a protective mask, a semiconductor device of 請 Motomeko 6, wherein that use resist film. Method for producing a to form a groove, the semiconductor device of 請 Motomeko 6 or 7, wherein Ru by wet blasting. Method for producing a to form a groove, the semiconductor device of 請 Motomeko 6 or 7, wherein Ru using etching. The first insulating layer and the second insulating layer, a method of manufacturing a semiconductor device according to any one of claims 6-9 configured to include either or both of polyimide and polyimide-based compounds.

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