JP4933792B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 71
- 238000004519 manufacturing process Methods 0.000 title claims description 29
- 230000015556 catabolic process Effects 0.000 claims description 66
- 239000000758 substrate Substances 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 19
- 238000002955 isolation Methods 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 92
- 229910052814 silicon oxide Inorganic materials 0.000 description 92
- 238000009792 diffusion process Methods 0.000 description 27
- 229910052710 silicon Inorganic materials 0.000 description 15
- 239000010703 silicon Substances 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 11
- 238000005530 etching Methods 0.000 description 10
- 150000004767 nitrides Chemical class 0.000 description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
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Description
図1は、全体が100で表される、本発明の実施の形態1にかかる半導体装置の断面図である。半導体装置100は、横型MOSトランジスタ(高耐圧素子)が設けられた高耐圧素子領域110と、CMOSトランジスタ(低耐圧素子)が設けられた低耐圧素子領域120とを含む。
なお、図2において、左側に高耐圧素子領域110、右側に低耐圧素子領域120を示す。
また、シリコン酸化膜12のパターニングは、ウエットエッチングを用いて行う。シリコン酸化膜12とシリコン酸化膜9a、9bとのエッチングレートの比(シリコン酸化膜12のエッチング速度/シリコン酸化膜9a、9bのエッチング速度)が2〜3程度となるようなエッチング条件を用い、シリコン酸化膜9a、9bのオーバーエッチングを防止する。
図4は、全体が200で表される、本発明の実施の形態2にかかる半導体装置の断面図である。半導体装置200は、MOSトランジスタ(高耐圧素子)が設けられた高耐圧素子領域210と、CMOSトランジスタ(低耐圧素子)が設けられた低耐圧素子領域220とを含む。図4において、図1と同一符号は、同一又は相当箇所を示す。
なお、図5において、左側に高耐圧素子領域210、右側に低耐圧素子領域220を示す。
図6は、全体が300で表される、本発明の実施の形態3にかかる半導体装置の断面図である。半導体装置300は、MOSトランジスタ(高耐圧素子)が設けられた高耐圧素子領域310と、CMOSトランジスタ(低耐圧素子)が設けられた低耐圧素子領域320とを含む。図6において、図1と同一符号は、同一又は相当箇所を示す。
なお、図7において、左側に高耐圧素子領域310、右側に低耐圧素子領域320を示す。
Claims (5)
- 高耐圧素子と低耐圧素子とを有する半導体装置であって、
該高耐圧素子が形成された高耐圧素子領域と、該低耐圧素子が形成された低耐圧素子領域とが規定された半導体基板と、
該高耐圧素子領域に設けられた第1LOCOS分離構造と、
該低耐圧素子領域に設けられた第2LOCOS分離構造とを含み、
該第1LOCOS分離構造が、該半導体基板の表面に形成されたLOCOS酸化膜と、その上に形成されたCVD酸化膜からなり、
該第2LOCOS分離構造が、LOCOS酸化膜からなり、
CVD酸化膜が、少なくとも下層CVD酸化膜とその上に形成された上層CVD酸化膜との積層構造からなり、該CVD酸化膜のエッジ部が、該下層CVD酸化膜および該上層CVD酸化膜から形成された階段形状であることを特徴とする半導体装置。 - 上記第1LOCOS分離構造に含まれるLOCOS酸化膜と、上記第2LOCOS分離構造に含まれるLOCOS酸化膜とが、ほぼ等しい膜厚であることを特徴とする請求項1に記載の半導体装置。
- 上記階段形状のエッジ部を覆うように、フィールドプレートが設けられたことを特徴とする請求項1に記載の半導体装置。
- 高耐圧素子と低耐圧素子とを有する半導体装置の製造方法であって、
該高耐圧素子が形成される高耐圧素子領域と、該低耐圧素子が形成される低耐圧素子領域とが規定された半導体基板を準備する工程、
該高耐圧素子領域と該低耐圧素子領域に、LOCOS酸化膜を形成する工程と、
該高耐圧素子領域のLOCOS酸化膜の上にCVD酸化膜を形成し、該LOCOS酸化膜と該CVD酸化膜からなる分離構造を形成するCVD工程とを含み、
該CVD工程が、
該LOCOS酸化膜の上に下層CVD酸化膜を形成し、該下層CVD酸化膜を熱処理する工程と、
該下層CVD酸化膜上に上層CVD酸化膜を形成する工程と、
該上層CVD酸化膜上に形成したマスクを用いて該上層CVD酸化膜と該下層CVD酸化膜をウエットエッチングし、該上層CVD酸化膜と該下層CVD酸化膜が階段状になったエッジ部を有する上記CVD酸化膜を形成する工程とを含むことを特徴とする半導体装置の製造方法。 - 上記高耐圧素子領域のLOCOS酸化膜と、上記低耐圧素子領域のLOCOS酸化膜とが、同一工程で形成されることを特徴とする請求項4に記載の製造方法。
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006037391A JP4933792B2 (ja) | 2006-02-15 | 2006-02-15 | 半導体装置及びその製造方法 |
US11/611,493 US8044487B2 (en) | 2006-02-15 | 2006-12-15 | Semiconductor device and method of manufacturing the same |
TW095147882A TWI323037B (en) | 2006-02-15 | 2006-12-20 | Semiconductor device and method of manufacturing the same |
CNB2007100063513A CN100514648C (zh) | 2006-02-15 | 2007-01-31 | 半导体装置及其制造方法 |
KR1020070012008A KR100847089B1 (ko) | 2006-02-15 | 2007-02-06 | 반도체장치 및 그 제조 방법 |
DE102007007096.0A DE102007007096B4 (de) | 2006-02-15 | 2007-02-13 | Halbleitervorrichtung und Verfahren zur Herstellung derselben |
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JP2006037391A JP4933792B2 (ja) | 2006-02-15 | 2006-02-15 | 半導体装置及びその製造方法 |
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JP2007220766A JP2007220766A (ja) | 2007-08-30 |
JP4933792B2 true JP4933792B2 (ja) | 2012-05-16 |
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US6858514B2 (en) * | 2002-03-29 | 2005-02-22 | Sharp Laboratories Of America, Inc. | Low power flash memory cell and method |
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KR20070082513A (ko) | 2007-08-21 |
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TW200733389A (en) | 2007-09-01 |
JP2007220766A (ja) | 2007-08-30 |
DE102007007096B4 (de) | 2017-08-24 |
CN100514648C (zh) | 2009-07-15 |
KR100847089B1 (ko) | 2008-07-18 |
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TWI323037B (en) | 2010-04-01 |
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