TWI323037B - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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TWI323037B
TWI323037B TW095147882A TW95147882A TWI323037B TW I323037 B TWI323037 B TW I323037B TW 095147882 A TW095147882 A TW 095147882A TW 95147882 A TW95147882 A TW 95147882A TW I323037 B TWI323037 B TW I323037B
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oxide film
withstand voltage
film
cvd
semiconductor device
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TW095147882A
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TW200733389A (en
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Satoshi Rittaku
Kazuhiro Shimizu
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Mitsubishi Electric Corp
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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Description

1323037 5 九、發明說明： 【發明所屬之技術領域】 本發明係關於-種半導體裝置及其製造方法，尤有關 於具備南耐壓元件與低耐壓元件之高耐壓IC等之半導體 裝置及其製造方法。 【先前技術】 近年來，高耐壓Ic (HVIC : High v〇ltage Ic)有非 _常令人驚嘆的進步。在此種高_ IC中，係將高耐壓元 件、控制電路及各種保護電路等之低耐壓元件形成於同一 晶片上。以高耐壓元件而言，係有例如橫型M〇s ( Μα" Oxide Silicon，金屬氧化半導體）電晶體等之利用降低表 - 面電場（Reduced Surface Field，RESURF)技術之元件屬 之，而以低耐壓元件而言，則有CM〇s( c〇mplementary M的d
Oxide Semiconductor，互補式金屬氧化半導體）或雙極性 電日日體（Bipolar Transistor)屬之0 第8圖係為以500表示整體，包括有高耐壓元件區域 510與低耐壓元件區域52〇之習知之半導體裝置（高耐壓 ic)之剖面圖，且為使用橫型n_chM0SFET作為高耐壓元 件、及使用CMOS電晶體作為低耐壓元件之例。半導體穿置 500係包括由石夕所構成的p半導體基板1。在半導體基板1 上，係形成有n+埋入擴散層2、η—磊晶層3。於磊晶層3 中’係形成有Ρ—擴散區域4、η+擴散區域5、ρ+擴散區域 6 ’而於蟲晶層3上則形成有多晶矽電極7、鋁電極8。於 2065-8545-PF 5 1323037 蟲晶層3上另形成有卩L〇c〇s ( 1〇cal 〇叫州加μ sil1C〇n，區域性矽氧化）法所形成之氧化矽膜9&、肋。 形成於低耐壓元件區域520之氧化矽膜9匕之膜厚係小於 形成於高耐壓元件區域510之氧化矽膜9a的膜厚其厚度 相當地薄。 【專利文獻】曰本特開昭64_77941號公報 【發明内容】 (發明所欲解決的課題） 然而，在半導體裝置500中，由於高耐壓元件區域51〇 與低耐壓元件區域520之製程未必相同，因此會有製造效 率變差，或高耐壓元件及低耐壓元件之特性降低的問題。 具體而言，於半導體装置5〇〇之高耐壓元件區域51〇 中，為使高耐壓元件具有穩定的高耐壓特性，必須緩和半 導體基板1之表面的電場強纟，而須有厚度較厚的氧化石夕 膜（LOCOS氧化膜）9a。另一方面，將L〇c〇s氧化膜形成 得較厚，會與半導體裝置的微細化、高積體化背道而驰而 使晶片尺寸增大。因此，在低耐壓元件區域52〇中，形成 作為元件間分離用之LOCOS氧化膜，只要於半導體基板i 的表面能確保反轉電壓即可，而盡可能希望使L〇c〇s氧化 膜的膜厚較薄《如此，在半導體裝置5〇〇中，於高耐壓元 件區域510與低耐壓元件區域52〇,即須有膜厚不同的氧 化矽膜（LOCOS氧化膜）9a、9b。 然而，為了要形成2種氧化矽臈（L〇c〇s氧化膜）9a、 2065-8545-PF 6 9b，須有2次的熱氧化製程，、 此外，在形成較厚的L〇c〇s氧：、程複雜化的問題。 的熱氧化，而會有在卿氣化=二且長_ 大，並且有擴散生之應力變 化的問題。 #貝擴^使半導體裝置之特性劣 纟明之目的在提供—#半導體裝置及其製造 二二、在具有高耐壓元件區域與低耐壓元件區域之半導 體裝置中’既確保高耐壓元件之高耐屋特性，又使高耐壓 兀件與低耐壓元件具有良好之特性者。 (用以解決課題的手段） 本發明係-種半導體裝置，具有高耐壓元件與低耐壓 元件’其特徵在於包括：半導體基板，規定有形成有高耐 壓兀件之高耐壓元件區域及形成有低耐壓元件之低耐壓元 :牛區域’第1 LOCOS分離結構’設於高耐壓元件區域；及 第2 LOCOS分離結構，設於低耐壓元件區域；第i l〇c〇s 刀離、”。構係由形成於半導體基板之表面的L〇c〇s氧化膜與 形成於J LOCOS氧化膜上之CVD氧化膜所構成；第2 L〇c〇s 分離結構係由LOCOS氧化膜所構成。 此外’本發明係一種半導體裝置之製造方法，該半導 體裝置具有咼耐壓元件與低对壓元件，其特徵在於包括： 準備半導體基板之步驟，該半導體基板規定有形成有高耐 壓元件之高耐壓元件區域及形成有低耐壓元件之低耐壓元 件區域；將LOCOS氧化膜形成於高耐壓元件區域與低耐壓 元件區域之步驟；及CVD步驟，將CVD氧化膜形成於高耐
2065-8545-PF 7 1323037 形成由L0C0S氧化膜與該 壓元件區域之LOCOS氧化膜上， CVD氧化膜所構成之分離結構。 (發明效果） 如此，在本發明令，係提供一種在具有高耐壓元件區 域與低㈣元件區域之半導㈣置中，具有良好特性的半 導體裝置。此外，此種半導體裝置可藉由簡單的製造方法 來製作。
【實施方式】 (實施形態1 ) 第1圖係為以1〇〇來表示整體之本發明之實施形態i 之半導體裝置之剖面圖。半導體裝置100係包括設有橫型 M0S電晶體（高耐壓元件）之高耐壓元件區域i丨〇及設有 CMOS電晶體（低耐壓元件）之低耐壓元件區域12〇。
半導體裝置1 00係包括p-矽基板！。於矽基板j上係 形成有π埋入擴散層2、η-遙晶層3。 在尚耐壓元件區域11 〇，係於磊晶層3中，設有構成 阱（well)區域之ρ擴散區域4。於擴散區域4之中係形 成有π擴政區域5與p +擴散區域6。n +擴散區域5與p + 擴散區域6係構成源極區域。此外，在磊晶層3的表面係 設有以LOCOS法形成之氧化矽膜9a作為分離元件之用。氧 化矽膜9a係與後述之低耐壓元件區域i 2〇之氧化矽膜9b 為相同之膜厚。 在氧化梦膜9a上係設有以CVD法形成之氧化石夕膜（cvd
2065-8545-PF i-323037 氧化膜）12。於磊晶声q 成有構成場板J 係、！由氧化m (未圖示）而形 _===—的多晶”極7。在多 緣層10上/切構成的絕緣層iG，且於該絕 丄你s又有銘電極8。叙雷 5 « n+4&, 電極8係連接於n +擴散區域 p擴政區域e而構成源極電極。在上 由風化石夕所構成的保護膜n。 有 在半導體裝置100中，如 卜 m
矽膜9b # π # + 上所述，乳化矽膜9a與氧化 ’膜9b係形成大略相同膜厚。 外兮罟铸儿a时 在乳化石夕膜9a上另 卜叹置巩化矽膜12，此等二個氧化 習知之半導體# w ςηη Λ 膜之膜居的總合，係與 化膜的膜 ：_ 於间耐壓兀件區域製作之LOCOS氧 、的臈厚為相同程度或更厚。 接著，參照第2圖說明半導體襄置⑽之 第2圖係為半導體裝置 、' 盥楚1 製之剖面圖，在第2圖中， ，、第1圖相同之符號，传g 係頌不相同或相等位置。此種製造 方法係包括以下的步驟丨至7。 在第2圖中’左側顯不高耐壓元件區域11 〇， 右側顯示低耐壓元件區域J20。 步驟1 :如第2圖（a)所示，於-、入彼，a。 、’所不於”夕基板1上形成n 埋入擴散層2。接著，形成η-磊曰 散法形成Ρ-擴散區域4。 日…’使用熱擴 步驟2:如第2圖（b)所示’在形成焊塾氧化膜（未 圖示）與氮化膜13之後’塗佈照相製版用的光阻。再者， 進行光阻的曝光、顯影，形成光阻遮罩14。接著，使用弁 阻遮罩U將氮化膜13進行圖案化。經由圖案化露出之半
2065-8545-PF 9 Ιό2όϋό/ 導體：板1之表面，係構成LOCOS氧化膜的形成區域。 罩且步驟3 :如第2圖（c)所示’將氮化膜13使用於遮 且將矽基板1選擇性氧化，而同時形成氧化矽膜 氧化膜）氧切膜9a與氧切膜％係形 相同膜厚。 v驟4.如第2圖（d)所示，將氮化膜13、焊墊氧化 膜（未圖示）去除。其結果’矽基板1的表面露出於氧化 矽膜仏、吒的周圍。 、乳化 步驟L如第2圖（e)所示’以覆蓋形成有氧化石夕膜 之矽基板1之表面之方式，形成氧化矽膜（氧 化膜_) 12。氧化石夕膜12係使用CVD法形成。接著，與步驟 2相同的步驟’形成照相製版用的光阻遮罩1 5。光阻遮罩 15係形成於氧化矽膜9a上方之氧化矽膜12上。 步驟6 .如第2圖（f)所示，使用光阻遮罩！ 5將氧 化石夕膜12進行圖案化，且將氧化石夕膜12殘留於氧化石夕膜
9a上。例如’氧化石夕膜（L〇c〇s敦化膜）^、⑽之膜厚，' 係設定為約刚至80_，而氧化石夕膜12之膜設 300 至 20〇〇nm。 &為 此外’氧切膜12之圖案化係使用濕㈣進行。兹使 用氧化石夕们2與氧化石夕膜9a、9k钱刻率的比值（氧化 ㈣12之㈣速度/氧切膜^、处之㈣速幻為2 至3左右的姓刻條件，防止氧化石夕膜Μ之過度姓刻。
步驟7:如第2圖（g)所示’經由氧化膜而 場板之多晶石夕電極7。另-方面，在高耐厂堅元件區域110 2065-8545-PF 10 叫3037 中’係形成分別構成_電晶體之P-chMOS f晶體及 n-chMOS電晶體之閘極電極，立形忐认
μ /、成於用以形成阱區域之P 擴散層4之上與矽基板1之上。
使用熱擴散法’選擇性形“+擴散區域5與P 擴散區域6之後，形成絕緣層 _ 站電極8、保護膜11 萼，即完成第1圖所示之半導體裝置1〇〇。 m ^此，在本實施形態丨之半導^置⑽之製造方法 因=11_法形成之氧化…之膜厚極薄， :此可防止在膽S氧化膜之邊緣部之應力的產生。此 外，由於保持於高溫的時間較短，因此亦可防 之雜質的擴散。其結果，可提 、月層中 體裝置1()0。 良好元件特性之半導 以二卜Γ須以個別的步驟來製作二種氧切膜9a、9b， 間早的步驟即可形成所希望之膜厚的氧化石夕膜。 第3圖係本發明之竇念
制妒 之貫施形態1之半導體裝置100之另 一製程之剖面圖，第3圖中，盥 之另 相同或相等位置。此種製…圖相同之符號係顯示 步驟i••如第:圖):法係包括以下的步驟。 2圖⑷至（c)):所示，以與上述步驟1至3(第 圆…至（〇 )相同的步驟，藉 遮罩之LOCOS法來形虬化膜13使用於 化胺” 氧化矽膜9a、9b。接著，在殘留氮 化膜13、焊墊氧化膜（未* 虱 形成氧化矽膜12。再者 ：，直接藉由CVD法 成於氧化矽膜9a上方之4 ㈣版用的光阻遮罩形 端部《與一重:::=2。上。先阻遮翠15係在
2065-8545-PF /驟2.如第3圖（b)所示，藉由使用光阻遮罩15 之濕㈣’將氧切膜12進行圖案化。錢刻係以將重疊 於氣化膜13之氧化石夕膜12藉由側面钱刻（sideetching) 去除之方式來進行。 乂驟3·如第3圖（c)所示’將光阻遮罩Η去除。 其結果’形成如第3圖（c )所示形狀之氧化矽膜12。 步驟4.如第3圖（d)所示，將氮化膜13、焊塾氧化 膜（未圖不）去除。接著，進行上述步驟7(第2圖（g)) 以後的步驟，藉此完成半導體裝置1〇〇。 依據此種製造方法，可防止在將氧化矽膜丨2進行濕蝕 刻之際，於氧化矽膜（LOCOS氧化膜）9a、9b之邊緣部的 減膜此外，由於在以氮化膜13將矽基板1之表面覆蓋的 狀態下將氧化矽膜12進行蝕刻，因此於蝕刻中，亦可保護 活性區域（元件形成區域）。 另外，在本實施形態1中，雖係以使用M0S電晶體作 為高耐壓元件，且以使用CM〇s電晶體作為低耐壓元件之情 形作說明，惟採用使用50至12〇〇v系的RESURF技術之絕 緣閘雙極電晶體（Insulated Gate Bip〇lar Transist〇r ; IGBT)作為高耐壓元件，或使用耐壓為3至4〇v左右之雙 極性電晶體作為低耐壓元件亦無妨（以下實施形態亦同）。 (實施形態2) 第4圖係為以2 0 0來表示整體之本發明之實施形態2 之半導體裝置之剖面圖。半導體裝置2〇〇係包括設有M〇s
2065-8545-PF 1.323037 電日日體（咼耐壓兀件）之高耐壓元 雷曰，牛&域21〇及設有CMOS 電日日體（低耐壓元件）之低耐 中，與第1圖相同之符笋孫在第4S 口々Μ之付號係顯不相同或相等位 在半導體裝置2 0 0令，係將以Γν 為多層結構12a、12bi邊緣料 Ρ之氧切膜設 成。再者，在該邊緣部上方，：::有蝴梯狀之方式形 ,,„ 你&成有多晶矽電極7。苴 、，·。果，形成場板（FP)之多晶矽 柚έ士播及如 位’即成為階梯狀。其
D構係與上述之半導體裝置100相同。 如此，在半導體裝置200中， 雪is 7 Λ、4 由於屯成％板之多晶矽 電極7成為階梯狀，因此於 端的埸刼彳Έ Τ/莖兀件之初段之場板（左 镔釦，品~r h 之表面之電場會階段性地 緩矛而可緩和局部性的電場隼中。& 以匕P m致 爷莱中另外，使用具有3層 以上之夕層結構之CVD氧化膜亦無妨。 接著’參照第5圖說明半導體裝置2〇〇之紫造方法。 第5圖係為半導體裝置 與第1圖相同之符於，#二 剖面圖，在第5圖中， 方法係包括以下的步驟。 以相專位置。此種製造 另外，在第5圖中，左側顯示高龍元件區域^ 〇， 右側顯示低耐壓元件區域22〇。 步驟i:在進行與上述第2圖（a)至（d)相同 驟之後，如第^ .接著，例如、二；；中㈣CVD法形成氧化石夕膜 在氣亂料中’進行90(TC、60分鐘的 熱處理。接著，以與氧化㈣心相_㈣條件 氣切膜12b。氧切膜12b不進行熱處理。氧切膜心
2065-8545-PF 13 1323037 们膜厚的總合，係以與實施形態1之氧化 12b、係、之膜尽相等之方式形成。氧化矽膜123肖氧化矽膜 ^係以大略相同之膜厚為佳。接著，形成照相製版用的 先阻遮罩15。光阻遮罩15係形成於氧化石夕膜9a上方 化矽膜12a、12b上。
步驟2·如第5圖（b)所示’使用光阻遮罩15將氧 化石夕膜12a、12b進行濕㈣卜在將氧切臈進行熱處理（燒 結收縮）時，氧切膜的膜質會變化，而使姓刻速度改變。 在此，於氧切膜12a與氧切膜12b中，膜的緻密性會 因為熱處理（燒結收縮）的有無而有所不同，而氧化石夕膜 12a的蝕刻速度，會變得比氧化矽膜12b的蝕刻速度慢。 因此，氧化矽膜12a、12b的邊緣部即成為階梯狀。於蝕刻 步驟後’將光阻遮罩14去除。 步驟3:如帛5圖（c)戶斤示，形成多晶石夕電極7。在 氧化矽膜12a、12b之邊緣部，多晶矽電極7亦形成階梯狀。 接著，藉由進行上述之第2圖（g)以後的步驟，即完成半 導體裝置200。 (實施形態3 ) 第6圖係為以30〇來表示整體之本發明之實施形態3 之半導體裝置之剖面圖。半導體裝置300係包括設有M〇s 電晶體（高耐壓元件）之高耐壓元件區域31 〇及設有cmos 電晶體（低耐壓元件）之低对壓元件區域32〇。在第6圖 中’與第1圖相同之符號係顯示相同或相等位置。 2065-8545-PF 14 1323037 在半導體裝置300中，係藉由CVD法而亦於低耐壓元 件區域320之氧化矽膜（L〇c〇s氧化膜）讥上形成有氧化 矽膜12b。其他結構係與實施形態！之半導體裝置1〇〇相 同。
低耐壓元件區域之氧化矽膜（L〇c〇s氧化膜）此係須 形成即使在將電壓施加於配置於該氧化矽膜（L〇c〇s氧化 膜）9b之上部之電極及配線時，氧化矽膜9b下部之矽基 板1之表面之電位亦不會反轉的厚度。 在本實施形態3之半導體裝置3〇〇中，由於係將氧化 矽膜12b疊層形成於氧化矽膜此上，因此可充分增大例如 鋁電極8與石夕基板丄之表面之距離，而可防止石夕基板上之 表面電位的反轉。《其即使是暫態大電壓施加☆銘電極8 時，仍能充分防止矽基板丨之表面之電位的反轉。其結果， 可提供可靠性高的半導體裝置3〇〇。 接著，參照第7圖說明半導體裝置3〇〇之製造方法。 第7圖係為半導體裝置_之製程之剖面圖，在第7圖中， 與第1圖相同之符號，係顯示相同或相等位置。此種製造 方法係包括以下的步驟。 另外’在第7圖+，左側顯示高耐壓元件區域310， 右側顯示低耐麼元件區域3 2 〇。
步驟1 :在進行與上述第2圖（a)至⑷相同之步 驟之後如第7圖（a)所示，使用CV])法形成氧化石夕膜 12。接著，形成照㈣版用的光阻遮罩…光阻遮罩心 係形成於高耐壓元件區域31〇之氧化石夕膜h上方之氧化矽 2065-8545-PF 15 丄:^Uj/ 腺 1 ? i- 及低耐塵元件區域320之氧化矽膜9b上方之氣 化矽膜12上之雙方。 ' .如第7圖（b)所示，使用光阻遮罩15將氧 ^ 2進行濕姓刻。其結果，在高耐壓元件區域31 〇之 乳化矽膜9a上方、及低耐壓元件區域320之氧化矽膜9b 上方之雙方’形成氧化矽膜12。 乂驟3.如第7圖（c)所示’形成多晶石夕電極7。接
著藉由進行上述之第2圖（g)以後的步驟，即完成半導 體裝置3 0 〇。 於本實施形態3之半導體裝置300之製造方法中，在 低耐壓兀件區域32〇中，氧化矽膜（LOCOS氧化膜）9b之 膜厚既可維持習知之較薄厚度，並且可增厚氧化石夕膜之總 、芬·（.氧化石夕膜9 b與氧化石夕膜12之膜厚的總合）。亦即， 由於可溥化氧化矽膜（LOCOS氧化膜）9b之膜厚，因此可 製造微細化、高積體化的半導體裝置300。 【圖式簡單說明】 第1圖係本發明之實施形態1之半導體裝置之剖面圖。 第2圖（a)〜（g )係本發明之實施形態1之半導體裝 置之製程之剖面圖。 第3圖（a )〜（d )係本發明之實施形態1之另一半導 體裝置之製程之剖面圖。 第4圖係本發明之實施形態2之半導體裝置之剖面圖。 第5圖（a)〜（c )係本發明之實施形態2之半導體裝
2065-8545-PF 16 1323037 置之製程之剖面圖。 第6圖係本發明之實施形態3之半導體裝置之剖面圖。 第7圖（a)〜（c)係本發明之實施形態3之半導體裝 置之製程之剖面圖。 第8圖係習知之半導體裝置之剖面圖。 【主要元件符號說明】
1硬基板、半導體基板 2 π埋入擴散層 3 η蟲晶層 4 Ρ—擴散區域 5. η擴散區域 6 Ρ+擴散區域 7多晶石夕電極 8 電極 9 氧化矽膜（L0C0S氧化膜） 9a、9b 氧化矽膜 10 絕緣膜 11保護膜 12 氧化矽膜（CVD氧化膜） 12a、12b多層結構 13氮化膜 14 光阻遮罩 15 光阻遮罩
2065-8545-PF 17 1001323037
110 120 200 210 220 300 310 500 510 520 半導體裝置 南耐壓7L件區域 低耐壓元件區域 半導體裝置 南耐壓元件區域 低耐壓元件區域 半導體裝置 1¾对壓件區域 低耐壓元件區域 半導體裝置 南耐壓7L件區域 低对壓70件區域
2065-8545-PF 18

Claims (1)

1323037 修正日期：99.1.13 第095147882號中文申請專利範圍修_ 十、申請專利範圍：&卿修正本 1. 一種半導體裝置，具有高耐壓元件與低耐壓元件， 其特徵在於包括： 半導體基板，規定有形成有高耐壓元件之高耐壓元件 區域及形成有低耐壓元件之低耐壓元件區域； 第1 L0C0S分離結構，設於高耐壓元件區域；及 第2 L0C0S分離結構，設於低耐壓元件區域；
該第1 L0C0S分離結構係由形成於該半導體基板之表 面的L0C0S氧化膜與形成於該L0C0S氧化膜上之CVD氧化 膜所構成； 該第2 L0C0S分離結構係由L0C0S氧化膜所構成； 上述CVD氧化膜係至少由下層CVD氧化膜與形成於該 CVD氧化膜上之上層CVD氧化膜之疊層結構所構成，該CVD 氧化膜之邊緣部係為由該下層CVD氧化膜及該上層CVD氧 化膜所形成之階梯形狀。 2. 如申請專利範圍第1項所述的半導體裝置，其中包 含於上述第1 L0C0S分離結構之L0C0S氧化膜與包含於上 述第2 L0C0S分離結構之L0C0S氧化膜係為大致相等的膜 厚。 3. 如申請專利範圍第1或2項所述的半導體裝置，其 中設有場板俾覆蓋上述階梯形狀的邊緣部。 4. 如申請專利範圍第1或2項所述的半導體裝置，其 中上述第2 L0C0S分離結構係於上述L0C0S氧化膜上更具 備有CVD氧化膜。 2065-8545-PF1 19 1323037 5. —種半導體裝置之製造方法’該半導體裝置具有高 耐壓元件與低耐壓元件， 其特徵在於包括： 準備半導體基板之步驟，該半導體基板規定有形成有 1¾封麼元件之高耐盧元件區域及形成有低耐壓元件之低耐 壓元件區域； 將L0C0S氧化膜形成於該高耐壓元件區域與該低耐壓 元件區域之步驟；及 CVD步驟’將CVD氧化膜形成於該高耐壓元件區域之 L0C0S氧化膜上，形成由該L〇c〇s氧化膜與該cvd氧化膜 所構成之分離結構；其中 上述CVD步驟係包括： 在形成上述L0C0S氧化膜之際，將上述cyD氧化膜形 成於覆蓋上述半導體基板之表面的氮化膜上之步驟；/ 使用形成於該CVD氧化膜上之遮罩將該㈣氧化膜進 行姓刻，且以使周圍重疊於該氮化膜之方.式殘留該aD 化膜之步驟；及 武 ，並將與該氮化膜重叠 法’該半導體裝置具有 之 將該CVD氧化膜進行濕蝕刻 部分的該CVD氧化膜予以去除。 6. 一種半導體裝置之製造方 耐壓元件與低耐壓元件， 其特徵在於包括： 平備午導體基板之步 ^ _丄 該半導體基板規定有形成 尚耐壓兀件之高耐壓元件 叶L埤及形成有低耐壓元件之佃 2065-8545-PF1 20 1323037 壓元件區域； 將LOCOS氧化膜形成於該高耐壓元件區域與該低耐壓 元件區域之步驟；及 CVD步驟，將CVD氧化膜形成於該高耐壓元件區域之 L0C0S氧化膜上，形成由該L0C0S氧化膜與該CVD氧化膜 所構成之分離結構；其中 上述CVD步驟係包括：
將下層CVD氧化膜形成於上述L0C0S氧化膜上，且將 該下層CVD氧化膜進行熱處理之步驟； 將上層CVD氧化膜形成於該下層CVD氧化膜上之步 驟；及 使用形成於該上層CVD氧化膜上之遮罩將該上層CVD 氧化膜與該下層CVD氧化膜進行濕蝕刻，形成具有由該上 層CVD氧化膜與該下層CVD氧化膜成為階梯狀之邊緣部之 上述CVD氧化膜之步驟。 7. 如申請專利範圍第5或6項所述的製造方法，其中 更包括將CVD氧化膜形成於上述低耐壓元件區域之L0C0S 氧化膜上。 8. 如申請專利範圍第5或6項所述的製造方法，其中 上述高耐壓元件區域之L0C0S氧化膜與上述低耐壓元件區 域之L0C0S氧化膜係由相同步驟所形成。 2065-8545-PF1 21 1323037 第095147882號中文圖式修正頁修正曰期：99.1 年|月&日修($正替換頁 110 120
第1圖 100 1333037 ^ 第095147882號中文圖式修正頁 修正曰期：99.1.13 • _ ^年丨月丨巧修(X)正替換頁 510 520
\ 、500 ' 第8圖
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