CN101022109A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN101022109A
CN101022109A CNA2007100063513A CN200710006351A CN101022109A CN 101022109 A CN101022109 A CN 101022109A CN A2007100063513 A CNA2007100063513 A CN A2007100063513A CN 200710006351 A CN200710006351 A CN 200710006351A CN 101022109 A CN101022109 A CN 101022109A
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film
voltage element
withstand voltage
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oxide
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CN100514648C (zh
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立宅聪
清水和宏
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Mitsubishi Electric Corp
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Abstract

提供一种在确保高耐压元件的高耐压特性的同时使高耐压元件和低耐压元件具有良好特性的半导体装置。具有高耐压元件和低耐压元件的半导体装置包含：规定了形成高耐压元件的高耐压元件区和形成低耐压元件的低耐压元件区的半导体衬底；在该高耐压元件区设置的第一LOCOS隔离结构；以及在该低耐压元件区设置的第二LOCOS隔离结构。第一LOCOS隔离结构由在该半导体衬底的表面上形成的LOCOS氧化膜和其上形成的CVD氧化膜构成，第二LOCOS隔离结构由LOCOS氧化膜构成。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体装置及其制造方法，特别是涉及设有高耐压元件和低耐压元件的高耐压IC等的半导体装置及其制造方法。
背景技术
近年来，高耐压IC(HVIC：高耐压IC)进步显著。在这样的高耐压IC中，在同一芯片上形成高耐压元件和控制电路及各种保护电路等低耐压元件。作为高耐压元件，例如有横式MOS晶体管等使用RESURF技术的元件，作为低耐压元件有CMOS晶体管和双极型晶体管。
图8是整体用500表示的包含高耐压元件区510和低耐压元件区的传统半导体装置(高耐压IC)的剖面图，作为高耐压元件的示例使用横式n沟道MOSFET，作为低耐压元件的示例使用CMOS晶体管。半导体装置500，包含由硅组成的p-半导体衬底1。在半导体衬底1上，形成n+掩埋扩散层2、n-外延层3。在外延层3中，形成p-扩散区4、n+扩散区5、p+扩散区6，在外延层3上形成多晶硅电极7、铝电极8。此外，在外延层3上，还用LOCOS法形成硅氧化膜9a、9b。在低耐压元件区520上形成的硅氧化膜9b的膜厚比在高耐压元件区510上形成的硅氧化膜9a充分地薄。
专利文献1：特开昭64-77941号公报
发明内容
但是，在半导体装置500上，有高耐压元件区510和低耐压元件区520的制造工序不一定一样，所以有不是制造效率恶化，就是高耐压元件和低耐压元件特性下降的问题。
具体地说，在半导体装置500上，为了使高耐压元件具有稳定高耐压特性，在高耐压元件区510必须缓和半导体衬底1的表面电场强度，比较厚的硅氧化膜(LOCOS氧化膜)9a是必要的。另一方面，若形成厚的LOCOS氧化膜，则违反半导体装置的微型化、高集成(的要求)使芯片尺寸增大。因此，在低耐压元件区520，为元件间隔离而形成的LOCOS氧化膜。若能确保半导体衬底1的表面上的反相电压就足够了，LOCOS氧化膜的膜厚最好尽可能薄。这样，在半导体装置500上，在高耐压元件区510和低耐压元件区520就必须形成膜厚不同的硅氧化膜(LOCOS氧化膜)9a、9b。
但是，为了形成2种硅氧化膜(LOCOS氧化膜)9a、9b，必须进行两次热氧化工序，存在使制造工序复杂化的问题。此外，形成厚的LOCOS氧化膜时，需在高温下进行长时间的热氧化，还有在LOCOS氧化膜的边缘部分发生的应力增大，而同时扩散层中的杂质扩散，使半导体装置的特性恶化的问题。
因此，本发明之目的在于，在具有高耐压元件区和低耐压元件区的半导体装置中确保高耐压元件的高耐压特性，同时提供高耐压元件和低耐压元件都具有良好特性的半导体装置及其制造方法。
本发明是一种半导体装置，其特征在于，它是具有高耐压元件和低耐压元件的半导体装置，包含：规定了形成高耐压元件的高耐压元件区和形成低耐压元件的低耐压元件区的半导体衬底；在高耐压元件区设置的第一LOCOS隔离结构；以及在低耐压元件区设置的第二LOCOS隔离结构，第一LOCOS隔离结构由在半导体衬底表面上形成的LOCOS氧化膜和在其上形成的CVD氧化膜组成，第二LOCOS隔离结构由LOCOS氧化膜组成。
此外，本发明也是半导体装置的制造方法，其特征在于，它是具有高耐压元件和低耐压元件的半导体装置的制造方法，包含：准备规定形成高耐压元件的高耐压元件区和形成低耐压元件的低耐压元件区的半导体衬底的工序；在高耐压元件区和低耐压元件区形成LOCOS氧化膜的工序；在高耐压元件区的LOCOS氧化膜上形成CVD氧化膜，形成由LOCOS氧化膜和该CVD氧化膜组成的隔离结构的工序。
这样，在本发明中，在具有高耐压元件区和低耐压元件区的半导体装置中，可以提供具有良好特性的半导体装置。此外，可以用简单的制造方法制作这样的半导体装置。
附图说明
图1是本发明实施例1的半导体装置的剖面图；
图2是发明的实施例1的半导体装置的制造工序剖面图；
图3是本发明实施例1的半导体装置的其余制造工序的剖面图；
图4是本发明实施例2的半导体装置的剖面图；
图5是本发明的实施例2的半导体装置的制造工序的剖面图；
图6是本发明的实施例3的半导体装置的剖面图；
图7是本发明实施例3的半导体装置的制造工序的剖面图；而
图8是传统半导体装置的剖面图。
附图标记说明
1硅衬底；2n+掩埋扩散层；3外延层；4p扩散区；5n+扩散区；6p+扩散区；7多晶硅电极；8铝电极；9硅氧化膜(LOCO氧化膜)；10绝缘膜；11保护膜；12硅氧化膜(CVD氧化膜)；100半导体装置；110高耐压元件区；120低耐压元件区。
具体实施方式
实施例1
图1是整体用100标示的本发明实施例1的半导体装置的剖面图。半导体装置100包含设置横式MOS晶体管(高耐压元件)的高耐压元件区110和设置CMOS晶体管(低耐压元件)的低耐压元件区120。
半导体装置100包含p-硅衬底1。在硅衬底1上，形成n+掩埋扩散层2和n-外延层3。
在高耐压元件区110，在外延层3中，设置成为阱区的p-扩散区4。在扩散区4中，形成n+扩散区5和p+扩散区6。n+扩散区5和p+扩散区6成为源极区。此外，在外延层3的表面上，为隔离元件而设置用LOCOS法形成的硅氧化膜9a。硅氧化膜9a，与后述低耐压元件区120的硅氧化膜9b膜厚相同。
硅氧化膜9a上，设置用CVD法形成的硅氧化膜(CVD氧化膜)12。在外延层3上，隔着氧化膜(图中未示出)形成成为场板的多晶硅电极7。在多晶硅电极7上，设置由氧化硅组成的绝缘层10，其上设置铝电极8。铝电极8与n+扩散区5以及p+扩散区6连接，成为源极电极。在铝电极8上，设置由氮化硅组成的保护膜11。
在半导体装置100中，如上所述，硅氧化膜9a和硅氧化膜9b膜厚大致相同。此外，在硅氧化膜9a上用其他方法设置硅氧化膜12，它们两者的氧化膜的膜厚合计，与在传统半导体装置500中在高耐压元件区制作的LOCOS氧化膜的膜厚大致相同或更厚。
接着，参照图2就半导体装置100的制造方法作一说明。图2是半导体装置100的制造工序的剖面图，在图2中与图1相同的符号表示相同或相当的部位。这样的制造方法包含以下工序1～7。
再有，在图2中，左侧表示高耐压元件区110，右侧表示低耐压元件区120。
工序1：如图2(a)所示，在p-硅衬底1上，形成n+掩埋扩散层2。接着，形成n-外延层3。此外，用热扩散法形成p-扩散层4。
工序2：如图2(b)所示，形成焊盘氧化膜(图中未示出)和氮化膜13后，涂敷照相制版用的光致抗蚀剂。此外，进行光致抗蚀剂的曝光、显影，形成抗蚀剂掩模14。接着，使用抗蚀剂掩模14使氮化膜13形成图案。由于形成图案而露出的半导体衬底1表面成为LOCOS氧化膜形成区。
工序3：如图2(c)所示，用氮化膜13作为掩模，选择性地氧化硅衬底1，同时形成硅氧化膜(LOCOS氧化膜)9a、9b。硅氧化膜9a和硅氧化膜9b的膜厚大致相同。
工序4：如图2(d)所示，除去氮化膜13和焊盘氧化膜(图中未示出)。结果，在硅氧化膜9a、9b的周围，露出硅衬底1的表面。
工序5：如图2(e)所示，形成硅氧化膜(CVD氧化膜)12，使之覆盖形成了硅氧化膜9a、9b的硅衬底1的表面。用CVD法形成硅氧化膜12。接着，在与工序2相同的工序中，形成照相制版用的抗蚀剂掩模15。抗蚀剂掩模15在硅氧化膜9a上方的硅氧化膜12上形成。
工序6：如图2(f)所示，用抗蚀剂掩模15使硅氧化膜12形成图案，在硅氧化膜9a上留下硅氧化膜12。例如，硅氧化膜(LOCOS氧化膜)9a、9b的膜厚设为约100～800nm，硅氧化膜12的膜厚设为300～2000nm。
此外，用湿蚀刻使硅氧化膜12形成图案。采用使硅氧化膜12和硅氧化膜9a、9b的蚀刻速率(硅氧化膜12的蚀刻速度和硅氧化膜9a、9b的蚀刻速度)之比约为2～3的蚀刻条件，防止硅氧化膜9a、9b的过蚀刻。
工序7：如图2(g)所示，隔着氧化膜形成成为场板的多晶硅电极7。另一方面，在低耐压元件区110，则在形成阱区的p-扩散层4上和在硅衬底1上形成，分别得到构成CMOS晶体管的p沟道MOS晶体管和n沟道MOS晶体管的栅极电极。
接着，用热扩散法选择性地形成n+扩散区5和p+扩散区6后，形成绝缘层10、铝电极7和保护膜11等，完成图1所示的半导体装置。
这样，由于在本实施例1的半导体装置100的制造方法中，用LOCOS法形成的硅氧化膜9a、9b的膜厚非常薄，可以防止LOCOS氧化膜的边缘部分中产生应力。此外，由于在高温下保持的时间短，还可以防止扩散层中杂质的扩散。结果，便有可能提供具有良好元件特性的半导体装置100。
此外，也没有必要在不同的工序中制作2种硅氧化膜9a、9b，可以用简单的工序形成所希望膜厚的硅氧化膜。
图3是本实施例1的半导体装置100的另一种制造工序的剖面图，在图3中，与图1相同的符号表示相同或相当的部位。这样的制造方法包含以下的工序。
工序1：如图3(a)所示，通过与上述工序1～3(图2(a)～(c))相同的工序，以氮化膜13作掩模用LOCOS法形成硅氧化膜9a、9b。接着，在氮化膜13、焊盘氧化膜(图中未示出)原样保留的情况下，用CVD法形成硅氧化膜12。此外，在硅氧化膜9a上方的硅氧化膜12上形成照相制版用的抗蚀剂掩模15。抗蚀剂掩模15在端部形成，与氮化膜13重叠。
工序2：如图3(b)所示，通过使用抗蚀剂掩模15的湿蚀刻使硅氧化膜12形成图案。进行湿蚀刻，用侧蚀刻除去重叠在氮化膜13上的硅氧化膜12。
工序3：如图3(c)所示，除去抗蚀剂掩模15。结果，形成图3(c)所示形状的硅氧化膜12。
工序4：如图3(d)所示，除去氮化膜13和焊盘氧化膜(图中未示出)。接着，进行上述工序7(图2(g))以后的工序完成半导体装置100。
采用这样的制造方法，可以防止湿蚀刻硅氧化膜12时硅氧化膜(LOCOS氧化膜)9a、9b的边缘部分中膜的减少。此外，由于在用氮化膜13覆盖硅衬底1表面的状态下蚀刻硅氧化膜12，因此在蚀刻中也可保护活性区(元件形成区)。
再有，在本实施例1中，叙述了用MOS晶体管作为高耐压元件，用CMOS晶体管作为低耐压元件的情况，也可以将采用50～1200V系列的RESURF技术的IGBT作为高耐压元件，用耐压3～40V左右的双极型晶体管作为低耐压元件(以下的实施例也一样)。
实施例2
图4是整体用200标示的本发明实施例2的半导体装置的剖面图。半导体装置200，包含设置了MOS晶体管(高耐压元件)的高耐压元件区210和设置了CMOS晶体管(低耐压元件)的低耐压元件区220。在图4中，与图1相同的符号表示相同或相当的部位。
在半导体装置200中，将用CVD形成的硅氧化膜作为多层结构12a、12b，边缘部分形成阶梯状。然后，在其上形成多晶硅电极7。结果，形成场板(FP)的多晶硅电极成为阶梯状。其余结构与上述的半导体装置100相同。
这样，在半导体装置200中，由于形成场板的多晶硅电极7成为阶梯状，在高耐压元件第一级的场板(左端的场板)上，直接下方的硅衬底1表面上的电场分阶段地缓和，可以缓和局部电场集中。另外，也可以使用具有3层以上多层结构的CVD氧化膜。
接着，参照图5就半导体装置200的制造方法作一说明。图5是半导体装置200制造工序的剖面图，在图5中，与图1相同的符号表示相同或相当的部位。这样的制造方法包含以下的工序。
再有，在图5中，左侧表示高耐压元件区210，右侧表示低耐压元件区220。
工序1：与上述图2(a)～(d)相同的工序后，如图5(a)所示，用CVD法形成硅氧化膜12a。接着，例如，在氮气氛中在900℃下进行60分钟的热处理。接着，在与硅氧化膜12a相同的CVD条件下，形成硅氧化膜12b。硅氧化膜12b不进行热处理。硅氧化膜12a和硅氧化膜12b的膜厚之和形成得与实施例1的硅氧化膜12的膜厚相等。硅氧化膜12a和硅氧化膜12b的膜厚最好大致相同。接着，形成照相制版用的抗蚀剂掩模15。抗蚀剂掩模15在硅氧化膜9a上方的硅氧化膜12a、12b上形成。
工序2：如图5(b)所示，用抗蚀剂掩模15湿蚀刻硅氧化膜12a、12b。硅氧化膜进行热处理(烧结)时，硅氧化膜的膜质改变，蚀刻速度改变。在这里，在硅氧化膜12a和硅氧化膜12b上，由于热处理(烧结)的有无，膜的致密度不同，硅氧化膜12a的蚀刻速度比硅氧化膜12b的蚀刻速度慢。因此，硅氧化膜12a、12b的边缘部分呈阶梯状。蚀刻工序后，除去抗蚀剂掩模14。
工序3：如图5(c)所示，形成多晶硅电极7。在硅氧化膜12a、12b的边缘部分，多晶硅电极7也成为阶梯状。接着，进行上述的图2(g)以后的工序，完成半导体装置200。
实施例3
图6是整体用300标示的本发明实施例3的半导体装置的剖面图。半导体装置300包含设置了MOS晶体管(高耐压元件)的高耐压元件区310和设置了CMOS晶体管(低耐压元件)的低耐压元件区320。在图6中，与图1相同的符号表示相同或相当的部位。
在半导体装置300中，在低耐压元件区320的硅氧化膜(LOCOS氧化膜)9b上还用CVD法形成硅氧化膜12b。其余结构与实施例1的半导体装置100相同。
低耐压元件区的硅氧化膜(LOCOS氧化膜)9b有必要形成足够的厚度，使得即使对配置在其上部的电极和布线施加电压时，硅氧化膜9b下部硅衬底1的表面电位也不反相。
在本实施例3的半导体装置300中，在硅氧化膜9b上由于层叠形成硅氧化膜12b，例如，可以充分增大铝电极8和硅衬底1表面的距离，可以防止硅衬底1的表面电位反相。特别是，即使在铝电极8上施加过大的电压的情况下，也可以充分地防止硅衬底1表面电位的反相。结果，可以提供可靠性高的半导体装置300。
接着，参照图7就半导体装置300的制造方法作一说明。图7是半导体装置300的制造工序的剖面图。在图7中，与图1相同的符号表示相同或相当的部位。这样的制造方法包含以下工序。
再有，在图7中，左侧表示高耐压元件区310，而右侧表示低耐压元件区320。
工序1：与上述图2(a)～(d)相同的工序之后，如图7(a)所示，用CVD法形成硅氧化膜12。接着，形成照相制版用的抗蚀剂掩模15。在高耐压元件区310硅氧化膜9a上方的硅氧化膜12上以及在低耐压元件区320的硅氧化膜9b上方的硅氧化膜12上都形成抗蚀剂掩模15。
工序2：如图7(b)所示，用抗蚀剂掩模，湿蚀刻硅氧化膜12。结果，在高耐压元件区310的硅氧化膜9a上方以及在低耐压元件区320的硅氧化膜9b上方都形成硅氧化膜12。
工序3：如图7(c)所示，形成多晶硅电极7。接着，进行上述图2(g)以后的工序，完成半导体装置300。
在本实施例3的半导体装置300的制造方法中，在低耐压元件区320上，硅氧化膜(LOCOS氧化膜)9b的膜厚维持以前一样薄，而同时硅氧化膜的总膜厚(硅氧化膜9b和硅氧化膜12的膜厚之和)可以变厚。就是说，由于硅氧化膜(LOCOS氧化膜)9b的膜厚可以薄，微型化、高度集成的半导体装置300的制造变得可能。

Claims (10)

1.一种半导体装置，其特征在于，它是具有高耐压元件和低耐压元件的半导体装置，包含：
规定了形成该高耐压元件的高耐压元件区和形成该低耐压元件的低耐压元件区的半导体衬底；
在该高耐压元件区设置的第一LOCOS隔离结构；以及
在该低耐压元件区设置的第二LOCOS隔离结构，
该第一LOCOS隔离结构由在该半导体衬底的表面上形成的LOCOS氧化膜和其上形成的CVD氧化膜构成，
该第二LOCOS隔离结构由LOCOS氧化膜构成。
2.权利要求1所述的半导体装置，其特征在于，包含于所述第一LOCOS隔离结构的LOCOS氧化膜和包含于所述第二LOCOS隔离结构的LOCOS氧化膜的膜厚大致相等。
3.权利要求1或2所述的半导体装置，其特征在于，所述CVD氧化膜至少由下层CVD氧化膜和其上形成的上层CVD氧化膜的层叠构造形成，该CVD氧化膜的边缘部分为由该下层CVD氧化膜和该上层CVD氧化膜形成的阶梯形状。
4.权利要求3所述的半导体装置，其特征在于，设置场板以覆盖所述阶梯形状的边缘部分。
5.权利要求1或2所述的半导体装置，其特征在于，所述第二LOCOS隔离结构中在所述LOCOS氧化膜上还设有CVD氧化膜。
6.一种半导体装置的制造方法，其特征在于，它是具有高耐压元件和低耐压元件的半导体装置的制造方法，包括：
准备规定了形成该高耐压元件的高耐压元件区和形成该低耐压元件的低耐压元件区的半导体衬底的工序；
在该高耐压元件区和该低耐压元件区形成LOCOS氧化膜的工序；以及
在该高耐压元件区的LOCOS氧化膜上形成CVD氧化膜，形成由该LOCOS氧化膜和该CVD氧化膜形成的隔离结构的CVD工序。
7.权利要求6所述的制造方法，其特征在于，所述CVD工序包括：
在形成所述LOCOS氧化膜时，在覆盖所述半导体衬底表面的氮化膜上形成所述CVD氧化膜的工序；
用在该CVD氧化膜上形成的掩模蚀刻该CVD氧化膜，在周围残留该CVD氧化膜以重叠在该氮化膜上的工序；以及
对该CVD氧化膜进行湿蚀刻而除去重叠在该氮化膜上的部分的CVD氧化膜的工序。
8.权利要求6所述的制造方法，其特征在于，所述CVD工序包含：
在所述LOCOS氧化膜上形成下层CVD氧化膜，并对该下层CVD氧化膜进行热处理的工序；
在该下层CVD氧化膜上形成上层CVD氧化膜的工序；
用在该上层CVD氧化膜上形成的掩模对该上层CVD氧化膜和该下层CVD氧化膜进行湿蚀刻，形成具有由该上层CVD氧化膜和该下层CVD氧化膜形成的阶梯状边缘部分的所述CVD氧化膜的工序。
9.权利要求6所述的制造方法，其特征在于，还包含在所述低耐压元件区的LOCOS氧化膜上形成CVD氧化膜的工序。
10.权利要求6～9中任何一项所述的制造方法，其特征在于，所述高耐压元件区的LOCOS氧化膜和所述低耐压元件区的LOCOS氧化膜在同一工序中形成。
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JP2004281966A (ja) 2003-03-19 2004-10-07 Ricoh Co Ltd 半導体装置及び半導体装置の製造方法
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* Cited by examiner, † Cited by third party
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CN103915334A (zh) * 2014-04-04 2014-07-09 中国电子科技集团公司第五十五研究所 高性能双层多晶硅双极型晶体管的制造方法
CN110137260A (zh) * 2019-05-23 2019-08-16 上海华虹宏力半导体制造有限公司 Ldmos晶体管的场氧化层隔离结构及其制备方法
CN110137260B (zh) * 2019-05-23 2022-05-10 上海华虹宏力半导体制造有限公司 Ldmos晶体管的场氧化层隔离结构及其制备方法

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KR100847089B1 (ko) 2008-07-18
CN100514648C (zh) 2009-07-15
TWI323037B (en) 2010-04-01
JP4933792B2 (ja) 2012-05-16
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TW200733389A (en) 2007-09-01
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