JP4920131B2 - 基板上のマイクロ構造あるいはナノ構造の製造方法 - Google Patents

基板上のマイクロ構造あるいはナノ構造の製造方法 Download PDF

Info

Publication number
JP4920131B2
JP4920131B2 JP2000504598A JP2000504598A JP4920131B2 JP 4920131 B2 JP4920131 B2 JP 4920131B2 JP 2000504598 A JP2000504598 A JP 2000504598A JP 2000504598 A JP2000504598 A JP 2000504598A JP 4920131 B2 JP4920131 B2 JP 4920131B2
Authority
JP
Japan
Prior art keywords
wafer
microstructure
nanostructure
crystal
lattice
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2000504598A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001511599A5 (https=
JP2001511599A (ja
Inventor
ミシェル・ブリュル
Original Assignee
コミッサリア ア レネルジー アトミーク エ オ ゼネルジ ザルタナテイヴ
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by コミッサリア ア レネルジー アトミーク エ オ ゼネルジ ザルタナテイヴ filed Critical コミッサリア ア レネルジー アトミーク エ オ ゼネルジ ザルタナテイヴ
Publication of JP2001511599A publication Critical patent/JP2001511599A/ja
Publication of JP2001511599A5 publication Critical patent/JP2001511599A5/ja
Application granted granted Critical
Publication of JP4920131B2 publication Critical patent/JP4920131B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Composite Materials (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)
JP2000504598A 1997-07-22 1998-07-20 基板上のマイクロ構造あるいはナノ構造の製造方法 Expired - Lifetime JP4920131B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR9709264A FR2766620B1 (fr) 1997-07-22 1997-07-22 Realisation de microstructures ou de nanostructures sur un support
FR97/09264 1997-07-22
PCT/FR1998/001585 WO1999005711A1 (fr) 1997-07-22 1998-07-20 Realisation de microstructures ou de nanostructures sur un support

Publications (3)

Publication Number Publication Date
JP2001511599A JP2001511599A (ja) 2001-08-14
JP2001511599A5 JP2001511599A5 (https=) 2011-01-20
JP4920131B2 true JP4920131B2 (ja) 2012-04-18

Family

ID=9509456

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000504598A Expired - Lifetime JP4920131B2 (ja) 1997-07-22 1998-07-20 基板上のマイクロ構造あるいはナノ構造の製造方法

Country Status (6)

Country Link
US (1) US6261928B1 (https=)
EP (1) EP1008169B1 (https=)
JP (1) JP4920131B2 (https=)
DE (1) DE69840480D1 (https=)
FR (1) FR2766620B1 (https=)
WO (1) WO1999005711A1 (https=)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19853023A1 (de) * 1998-11-18 2000-05-31 Forschungszentrum Juelich Gmbh Verfahren zur Herstellung von Nanostrukturen in dünnen Filmen
JP2003516241A (ja) * 1999-12-09 2003-05-13 コーネル・リサーチ・ファンデーション・インコーポレイテッド ナノメートル規模の間隔で周期的表面構造を製作する方法
FR2815026B1 (fr) * 2000-10-06 2004-04-09 Commissariat Energie Atomique Procede d'auto-organisation de microstructures ou de nanostructures et dispositif a microstructures ou a nanostructures
FR2815121B1 (fr) * 2000-10-06 2002-12-13 Commissariat Energie Atomique Procede de revelation de defauts cristallins et/ou de champs de contraintes a l'interface d'adhesion moleculaire de deux materiaux solides
FR2819099B1 (fr) * 2000-12-28 2003-09-26 Commissariat Energie Atomique Procede de realisation d'une structure empilee
US6913697B2 (en) 2001-02-14 2005-07-05 Science & Technology Corporation @ Unm Nanostructured separation and analysis devices for biological membranes
US6699770B2 (en) * 2001-03-01 2004-03-02 John Tarje Torvik Method of making a hybride substrate having a thin silicon carbide membrane layer
JP2002265831A (ja) * 2001-03-13 2002-09-18 Ricoh Co Ltd インク組成物及びそれを使用する記録方法
US7045878B2 (en) 2001-05-18 2006-05-16 Reveo, Inc. Selectively bonded thin film layer and substrate layer for processing of useful devices
US6956268B2 (en) 2001-05-18 2005-10-18 Reveo, Inc. MEMS and method of manufacturing MEMS
KR100425092B1 (ko) * 2001-05-29 2004-03-30 엘지전자 주식회사 실리콘 컴플라이언트 기판 제조방법
CN1164488C (zh) * 2001-07-25 2004-09-01 中山大学 一种纳米碳化硅材料的制备方法
US7163826B2 (en) 2001-09-12 2007-01-16 Reveo, Inc Method of fabricating multi layer devices on buried oxide layer substrates
US6875671B2 (en) 2001-09-12 2005-04-05 Reveo, Inc. Method of fabricating vertical integrated circuits
DE50205771D1 (de) * 2001-11-23 2006-04-13 Univ Duisburg Essen Implantat
JP2005279843A (ja) * 2004-03-29 2005-10-13 Univ Of Tokyo 細線を含む結晶材料とその製造方法、およびこれを用いたナノ細線デバイス
FR2876498B1 (fr) * 2004-10-12 2008-03-14 Commissariat Energie Atomique Procede de realisation d'heterostructures resonnantes a transport planaire
FR2877662B1 (fr) 2004-11-09 2007-03-02 Commissariat Energie Atomique Reseau de particules et procede de realisation d'un tel reseau.
FR2895391B1 (fr) * 2005-12-27 2008-01-25 Commissariat Energie Atomique Procede d'elaboration de nanostructures ordonnees
FR2895419B1 (fr) 2005-12-27 2008-02-22 Commissariat Energie Atomique Procede de realisation simplifiee d'une structure epitaxiee
FR2895571B1 (fr) * 2005-12-28 2008-04-18 Commissariat Energie Atomique Procede de realisation d'une jonction pn electroluminescente en materiau semi-conducteur par collage moleculaire
FR2896493B1 (fr) * 2006-01-23 2008-02-22 Commissariat Energie Atomique Procede d'elaboration d'un support pour la croissance de nanostructures allongees localisees
FR2903810B1 (fr) * 2006-07-13 2008-10-10 Commissariat Energie Atomique Procede de nanostructuration de la surface d'un substrat
JP2008060355A (ja) * 2006-08-31 2008-03-13 Sumco Corp 貼り合わせウェーハの製造方法および貼り合わせウェーハ
FR2925748B1 (fr) 2007-12-21 2010-01-29 Commissariat Energie Atomique Support de stockage de donnees et procede associe
FR2937797B1 (fr) * 2008-10-28 2010-12-24 S O I Tec Silicon On Insulator Tech Procede de fabrication et de traitement d'une structure de type semi-conducteur sur isolant, permettant de deplacer des dislocations, et structure correspondante
FR2978600B1 (fr) 2011-07-25 2014-02-07 Soitec Silicon On Insulator Procede et dispositif de fabrication de couche de materiau semi-conducteur
JP6355540B2 (ja) * 2014-12-04 2018-07-11 株式会社ディスコ ウエーハの生成方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
DE4133820A1 (de) * 1991-10-12 1993-04-15 Bosch Gmbh Robert Verfahren zur herstellung von halbleiterelementen
JP3237888B2 (ja) * 1992-01-31 2001-12-10 キヤノン株式会社 半導体基体及びその作製方法
JP3192000B2 (ja) * 1992-08-25 2001-07-23 キヤノン株式会社 半導体基板及びその作製方法
JP2908150B2 (ja) * 1992-11-27 1999-06-21 日本電気株式会社 Ｓｏｉ基板構造及びその製造方法
FR2714524B1 (fr) 1993-12-23 1996-01-26 Commissariat Energie Atomique Procede de realisation d'une structure en relief sur un support en materiau semiconducteur
FR2715502B1 (fr) 1994-01-26 1996-04-05 Commissariat Energie Atomique Structure présentant des cavités et procédé de réalisation d'une telle structure.
FR2715501B1 (fr) 1994-01-26 1996-04-05 Commissariat Energie Atomique Procédé de dépôt de lames semiconductrices sur un support.
JPH07263721A (ja) * 1994-03-25 1995-10-13 Nippondenso Co Ltd 半導体装置及びその製造方法
FR2725074B1 (fr) * 1994-09-22 1996-12-20 Commissariat Energie Atomique Procede de fabrication d'une structure comportant une couche mince semi-conductrice sur un substrat
US5932048A (en) * 1995-04-06 1999-08-03 Komatsu Electronic Metals Co., Ltd. Method of fabricating direct-bonded semiconductor wafers
JP3441277B2 (ja) * 1995-12-26 2003-08-25 株式会社東芝 半導体装置およびその製造方法
FR2756973B1 (fr) 1996-12-09 1999-01-08 Commissariat Energie Atomique Procede d'introduction d'une phase gazeuse dans une cavite fermee
US6159824A (en) * 1997-05-12 2000-12-12 Silicon Genesis Corporation Silicon-on-silicon wafer bonding process using a thin film blister-separation method
US5877070A (en) * 1997-05-31 1999-03-02 Max-Planck Society Method for the transfer of thin layers of monocrystalline material to a desirable substrate
US5882987A (en) * 1997-08-26 1999-03-16 International Business Machines Corporation Smart-cut process for the production of thin semiconductor material films
US5981400A (en) * 1997-09-18 1999-11-09 Cornell Research Foundation, Inc. Compliant universal substrate for epitaxial growth
US5897362A (en) * 1998-04-17 1999-04-27 Lucent Technologies Inc. Bonding silicon wafers

Also Published As

Publication number Publication date
FR2766620A1 (fr) 1999-01-29
JP2001511599A (ja) 2001-08-14
US6261928B1 (en) 2001-07-17
EP1008169A1 (fr) 2000-06-14
DE69840480D1 (de) 2009-03-05
WO1999005711A1 (fr) 1999-02-04
FR2766620B1 (fr) 2000-12-01
EP1008169B1 (fr) 2009-01-14

Similar Documents

Publication Publication Date Title
JP4920131B2 (ja) 基板上のマイクロ構造あるいはナノ構造の製造方法
US6569748B1 (en) Substrate and production method thereof
CN101401199B (zh) 含有连接表面层和衬底区域的部分soi结构制造方法
JP4954853B2 (ja) ２つの固体材料の分子接着界面における結晶欠陥および／または応力場の顕在化プロセス
EP2629320B1 (en) Mask structure and method for defect-free heteroepitaxial deposition
CN113330572B (zh) 量子装置的制作
JP4730877B2 (ja) 応力を低減して層転位を介して緩和シリコン−ゲルマニウムを絶縁体上に作製する方法
JP2001523049A (ja) 量子稜線および量子頂上
JPH0621336A (ja) 表面積が極大化されたシリコン層およびその製造方法
WO2007018495A2 (en) Method for controlling dislocation positions in silicon germanium buffer layers
JPH03165577A (ja) 半導体デバイスとその製造方法
US20010041419A1 (en) Method for fabrication semiconductor device having trench isolation structure
JP2023527123A (ja) イオン注入によるｓａｇナノワイヤ成長
JP3954095B2 (ja) マイクロ電子素子およびその製造方法
US20150179583A1 (en) Semiconductor devices comprising edge doped graphene and methods of making the same
JP3748726B2 (ja) 量子細線の製造方法
US7060587B2 (en) Method for forming macropores in a layer and products obtained thereof
TWI588886B (zh) 製造半導體裝置之方法
JP4309869B2 (ja) 半導体装置およびその製造方法
JP3789179B2 (ja) 量子化機能素子とそれを用いた量子化機能装置、ならびにそれらの製造方法
JP2643015B2 (ja) 完全誘電体分離基板の製造方法
US6905955B2 (en) Methods of forming conductive connections, and methods of forming nanofeatures
JPH08236748A (ja) 量子半導体装置及びその製造方法
JPH05235378A (ja) Ｓｉ半導体装置とその製造方法
JPH09135017A (ja) 量子デバイスの製造方法

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050707

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090623

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20090924

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20091001

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091224

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100525

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20100825

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20100901

A524 Written submission of copy of amendment under article 19 pct

Free format text: JAPANESE INTERMEDIATE CODE: A524

Effective date: 20101125

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110802

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20111101

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20111109

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111201

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20120104

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20120201

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20150210

Year of fee payment: 3

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term