JP4903434B2 - トレンチカット型(trenchcut)発光ダイオードおよびその製造方法 - Google Patents
トレンチカット型(trenchcut)発光ダイオードおよびその製造方法 Download PDFInfo
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- JP4903434B2 JP4903434B2 JP2005505523A JP2005505523A JP4903434B2 JP 4903434 B2 JP4903434 B2 JP 4903434B2 JP 2005505523 A JP2005505523 A JP 2005505523A JP 2005505523 A JP2005505523 A JP 2005505523A JP 4903434 B2 JP4903434 B2 JP 4903434B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
Description
Claims (19)
- 相対向する第1および第2の面を有する半導体基板と、第1および第2のデバイス部を含む、前記基板の第2の面上の少なくとも1つのデバイス層とを使用して半導体デバイスを形成する方法であって、
前記第1のデバイス部と第2のデバイス部との間の前記基板の前記第1の面に第1のトレンチを形成するステップと、
前記少なくとも1つのデバイス層内に、前記第1のデバイス部を含む第1のメサおよび前記第2のデバイス部を含む第2のメサの範囲を定める分離トレンチを形成するステップと、
前記基板の前記第2の面側の前記分離トレンチの中から前記基板へと伸びて前記第1のデバイス部と第2のデバイス部との間の前記基板の前記第2の面において第2のトレンチを形成するステップと、
前記第1のトレンチおよび前記第2のトレンチに沿って前記基板を切断して、前記基板の第1の部分および前記第1のデバイス部を含む第1のダイならびに前記基板の第2の部分および前記第2のデバイス部を含む第2のダイを形成するステップと、
を備え、前記第1のトレンチは少なくとも50μmの幅を有し、前記第2のトレンチは2〜25μmの幅を有する、
ことを特徴とする方法。 - 前記第1のトレンチは、前記基板において少なくとも100μmの深さを有することを特徴とする請求項1に記載の方法。
- デバイス面を有する半導体基板と、第1および第2のデバイス部を含む、前記基板のデバイス面上の少なくとも1つのデバイス層とを使用する半導体デバイスを形成する方法であって、
前記少なくとも1つのデバイス層内に、前記第1のデバイス部を含む第1のメサおよび前記第2のデバイス部を含む第2のメサの範囲を定める分離トレンチを形成するステップと、
前記第1および第2のメサ上に犠牲層を形成するステップと、
前記犠牲層が前記第1および第2のメサ上に配置されている間に、前記基板のデバイス面側の前記分離トレンチの中から前記基板へと伸びて前記第1のデバイス部と第2のデバイス部との間の前記基板のデバイス面において第2のトレンチを形成するステップと、
前記犠牲層を除去するステップと、
前記第2のトレンチに沿って前記基板を切断して、前記基板の第1の部分および前記第1のデバイス部を含む第1のダイならびに前記基板の第2の部分および前記第2のデバイス部を含む第2のダイを形成するステップと、を備えたことを特徴とする方法。 - 相対向する第1および第2の面を有する半導体基板と、第1および第2のデバイス部を含む、前記基板の第2の面上の少なくとも1つのデバイス層とを使用して半導体デバイスを形成する方法であって、
前記第1のデバイス部と前記第2のデバイス部との間の前記基板の前記第1の面において立方体の頂点を備えた角錐台を定めるように第1のトレンチを形成するステップと、
前記少なくとも1つのデバイス層内に、前記第1のデバイス部を含む第1のメサおよび前記第2のデバイス部を含む第2のメサの範囲を定める分離トレンチを形成するステップと、
前記基板の第2の面側の前記分離トレンチの中から前記基板へと伸びて前記第1のデバイス部と第2のデバイス部との間の前記基板の前記第2の面において第2のトレンチを形成するステップと、
前記第1のトレンチおよび前記第2のトレンチに沿って前記基板を切断して、前記基板の第1の部分および前記第1のデバイス部を含む第1のダイならびに前記基板の第2の部分および前記第2のデバイス部を含む第2のダイを形成するステップと、を備えることを特徴とする方法。 - 前記第1のトレンチは、前記基板において少なくとも100μmの深さを有することを特徴とする請求項4に記載の方法。
- 前記第1のトレンチは、前記基板において少なくとも200〜220μmの深さを有することを特徴とする請求項4に記載の方法。
- 前記第2のトレンチは、前記基板において少なくとも2〜5μmの深さを有し、前記第1のトレンチは、前記基板において少なくとも150〜200μmの深さを有することを特徴とする請求項4に記載の方法。
- デバイス面を有する半導体基板と、第1および第2のデバイス部を含む、前記基板のデバイス面上の少なくとも1つのデバイス層とを使用する半導体デバイスを形成する方法であって、
前記少なくとも1つのデバイス層内に、前記第1のデバイス部を含む第1のメサおよび前記第2のデバイス部を含む第2のメサの範囲を定める分離トレンチを形成するステップと、
前記基板のデバイス面側の前記分離トレンチの中から前記基板へと伸びて前記第1のデバイス部と第2のデバイス部との間の前記基板の前記デバイス面において第2のトレンチを形成するステップと、
前記第2のトレンチに沿って前記基板を切断して、前記基板の第1の部分および前記第1のデバイス部を含む第1のダイならびに前記基板の第2の部分および前記第2のデバイス部を含む第2のダイを形成するステップと、を備え、
前記第2のトレンチを形成するステップは、前記第2のトレンチを前記基板のデバイス面内にレーザースクライビングするステップで形成することを特徴とする方法。 - 前記第1および第2のダイは、それぞれ第1および第2の発光ダイオード(LED)又はそれぞれ第1及び第2のレーザダイオードを含むことを特徴とする請求項1、3、4又は8に記載の方法。
- 前記第2のトレンチに沿って前記第1および第2のメサの露出面と前記基板上とに電気絶縁性のパッシベーション層を形成するステップをさらに備えたことを特徴とする請求項1、3、8のいずれかに記載の方法。
- 前記分離トレンチを形成するステップは、少なくとも1つのデバイス層をエッチングするステップを含むことを特徴とする請求項1、3、8のいずれかに記載の方法。
- 前記第1および第2のデバイス部上に、それぞれ第1および第2のコンタクトを形成するステップをさらに備えたことを特徴とする請求項1乃至11のいずれかに記載の方法。
- 前記第2のトレンチを形成するステップに先立ち犠牲層を形成するステップと、前記第2のトレンチを形成するステップの後に前記犠牲層を除去するステップとをさらに備えたことを特徴とする請求項1乃至12のいずれかに記載の方法。
- 前記第2のトレンチを形成するステップは、ダイス加工、切断加工、エッチング、および/またはレーザースクライビングのうちの少なくとも1つの処理ステップを含むことを特徴とする請求項1乃至13のいずれかに記載の方法。
- 前記第2のトレンチを形成するステップは、前記基板の第2の面内に前記第2のトレンチをレーザースクライビングで形成するステップを含むことを特徴とする請求項14に記載の方法。
- 前記第2のトレンチを形成するステップは、前記基板の第2の面内に前記第2のトレンチを切断加工で形成するステップを含むことを特徴とする請求項14に記載の方法。
- 前記第1のトレンチを形成するステップは、前記第1のトレンチが立方体の頂点を備えた角錐台を定めるように前記第1のトレンチを切断加工するステップを含むことを特徴とする請求項1に記載の方法。
- 前記基板は、SiC、GaAs、GaP、サファイアおよびそれらの組み合わせから成る群から選択される材料で形成されることを特徴とする請求項1乃至17のいずれかに記載の方法。
- 前記少なくとも1つのデバイス層は、第III族窒化物を含むことを特徴とする請求項1乃至18のいずれかに記載の方法。
Applications Claiming Priority (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US39748802P | 2002-07-19 | 2002-07-19 | |
US60/397,488 | 2002-07-19 | ||
US41589802P | 2002-10-03 | 2002-10-03 | |
US60/415,898 | 2002-10-03 | ||
US10/610,329 | 2003-06-30 | ||
US10/610,329 US6995032B2 (en) | 2002-07-19 | 2003-06-30 | Trench cut light emitting diodes and methods of fabricating same |
PCT/US2003/022411 WO2004010510A2 (en) | 2002-07-19 | 2003-07-11 | Trench cut light emitting diodes and methods of fabricating same |
Publications (3)
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JP2006510232A JP2006510232A (ja) | 2006-03-23 |
JP2006510232A5 JP2006510232A5 (ja) | 2006-08-24 |
JP4903434B2 true JP4903434B2 (ja) | 2012-03-28 |
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JP2005505523A Expired - Lifetime JP4903434B2 (ja) | 2002-07-19 | 2003-07-11 | トレンチカット型(trenchcut)発光ダイオードおよびその製造方法 |
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US (2) | US6995032B2 (ja) |
EP (1) | EP1523768B1 (ja) |
JP (1) | JP4903434B2 (ja) |
KR (2) | KR20110017467A (ja) |
CN (1) | CN100375242C (ja) |
AU (1) | AU2003252005A1 (ja) |
MY (1) | MY138543A (ja) |
TW (1) | TWI283491B (ja) |
WO (1) | WO2004010510A2 (ja) |
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2005
- 2005-11-14 US US11/273,008 patent/US7368756B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
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WO2004010510A3 (en) | 2004-08-19 |
KR101098743B1 (ko) | 2011-12-23 |
CN100375242C (zh) | 2008-03-12 |
MY138543A (en) | 2009-06-30 |
EP1523768A2 (en) | 2005-04-20 |
EP1523768B1 (en) | 2017-04-12 |
KR20110017467A (ko) | 2011-02-21 |
WO2004010510A2 (en) | 2004-01-29 |
CN1679144A (zh) | 2005-10-05 |
TWI283491B (en) | 2007-07-01 |
US20060079082A1 (en) | 2006-04-13 |
JP2006510232A (ja) | 2006-03-23 |
US7368756B2 (en) | 2008-05-06 |
AU2003252005A8 (en) | 2004-02-09 |
US6995032B2 (en) | 2006-02-07 |
TW200417054A (en) | 2004-09-01 |
AU2003252005A1 (en) | 2004-02-09 |
WO2004010510A8 (en) | 2005-06-16 |
US20040051118A1 (en) | 2004-03-18 |
KR20050119635A (ko) | 2005-12-21 |
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