JP4888975B2 - チャネルアクセストランジスタおよび積層型蓄積キャパシタを備えた垂直dram装置および関連方法 - Google Patents
チャネルアクセストランジスタおよび積層型蓄積キャパシタを備えた垂直dram装置および関連方法 Download PDFInfo
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- JP4888975B2 JP4888975B2 JP2007241699A JP2007241699A JP4888975B2 JP 4888975 B2 JP4888975 B2 JP 4888975B2 JP 2007241699 A JP2007241699 A JP 2007241699A JP 2007241699 A JP2007241699 A JP 2007241699A JP 4888975 B2 JP4888975 B2 JP 4888975B2
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- 239000003990 capacitor Substances 0.000 title claims description 32
- 238000003860 storage Methods 0.000 title claims description 28
- 238000000034 method Methods 0.000 title description 9
- 125000006850 spacer group Chemical group 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 18
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 150000004767 nitrides Chemical class 0.000 claims 2
- 210000004027 cell Anatomy 0.000 description 49
- 229910052581 Si3N4 Inorganic materials 0.000 description 17
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 17
- 230000015572 biosynthetic process Effects 0.000 description 7
- 239000004065 semiconductor Substances 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000001154 acute effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000013341 scale-up Methods 0.000 description 1
- 210000000352 storage cell Anatomy 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Microelectronics & Electronic Packaging (AREA)
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- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Thin Film Transistor (AREA)
Description
Claims (10)
- 集積回路メモリ装置であって、
基板と、
セルアクセストランジスタと、
蓄積キャパシタを含み、
前記セルアクセストランジスタが、
前記基板に少なくとも一部沿って延伸する接続線と、
前記接続線に電気的に接続された導電的にドープされた下部ソース/ドレイン領域と、
前記導電的にドープされた下部ソース/ドレイン領域上に渡って配置され、チャネル領域を規定する導電的にドープされた上部ソース/ドレイン領域と、ここで、前記導電的にドープされた下部ソース/ドレイン領域、前記チャネル領域及び前記導電的にドープされた上部ソース/ドレイン領域はトランジスタピラーを形成し、
前記チャネル領域に近接する前記トランジスタピラーの表面上に配置されたゲート誘電体層及び導電ゲート層を含むゲートと、
前記上部ソース/ドレイン領域上に渡って配置され直接接触する導電性ソース/ドレイン層と、ここで、前記導電性ソース/ドレイン層は平面上部表面を有し、
前記導電性ソース/ドレイン層の側面と接触し、それに沿って下方に向かって延在した誘電体スペーサを含み、ここで、前記導電性ソース/ドレイン層の平面上部表面と前記誘電体スペーサの上部表面は同一平面を構成し、
前記蓄積キャパシタが前記導電性ソース/ドレイン層と電気的に接続し、前記蓄積キャパシタはさらに前記導電性ソース/ドレイン層の前記平面上部表面上に渡って配置される第1の部分と、前記誘電体スペーサに完全に沿って延伸し直接接触する第2の部分を有する
ことを特徴とする集積回路メモリ装置。 - 前記蓄積キャパシタは、
前記導電性ソース/ドレイン層の前記平面上部表面に隣接し、それに電気的に接続されている、第1の電極層と、
該第1の電極層に隣接する誘電体層と、
該誘電体層に隣接する第2の電極層と、
を含む請求項1記載の集積回路メモリ装置。 - 垂直方向に前記基板に隣接し横方向に前記ピラーに隣接する、少なくとも1つの下部誘電体層と、
垂直方向に該少なくとも1つの下部誘電体層の上方に間隔を空けて配置され、横方向に前記ピラーに隣接する、少なくとも1つの上部誘電体層とを含み、
前記ゲートは前記少なくとも一つの下部誘電体層と前記上部誘電体層の間にあることを特徴とする請求項1記載の集積回路メモリ装置。 - 前記ゲートは、チャネル領域に近接する前記ピラーの互いに対向する表面上に配置された第1のゲートと第2のゲートからなることを特徴とする請求項3記載の集積回路メモリ装置。
- 前記少なくとも一つの上部誘電体層が、前記ゲート上の酸化物層及び前記酸化物層上の窒化物層を含むことを特徴とする請求項4記載の集積回路メモリ装置。
- 集積回路メモリ装置を製造する方法であって、
セルアクセストランジスタを形成する工程と、ここで、前記セルアクセストランジスタは、
基板に少なくとも一部沿って延伸する接続線を形成し、
前記接続線に電気的に接続された導電的にドープされた下部ソース/ドレイン領域を形成し、
前記導電的にドープされた下部ソース/ドレイン領域上に渡って配置され、チャネル領域を規定する導電的にドープされた上部ソース/ドレイン領域を形成し、ここで、前記導電的にドープされた下部ソース/ドレイン領域、前記チャネル領域及び前記導電的にドープされた上部ソース/ドレイン領域はトランジスタピラーを形成し、
前記チャネル領域に近接する前記トランジスタピラーの表面上に配置されたゲート誘電体層及び導電ゲート層を含むゲートを形成し、
前記上部ソース/ドレイン領域上に渡って配置され直接接触する導電性ソース/ドレイン層を形成し、ここで、前記導電性ソース/ドレイン層は平面上部表面を有し、
前記導電性ソース/ドレイン層の側面と接触し、それに沿って下方に向かって延在した誘電体スペーサを形成する工程を含み、ここで、前記導電性ソース/ドレイン層の平面上部表面と前記誘電体スペーサの上部表面は同一平面を構成し、
前記蓄積キャパシタを前記導電性ソース/ドレイン層と電気的に接続する工程を含み、
前記蓄積キャパシタはさらに前記導電性ソース/ドレイン層の前記平面上部表面上に渡って配置される第1の部分と、前記誘電体スペーサに完全に沿って延伸し直接接触する第2の部分を有する
ことを特徴とする集積回路メモリ装置の製造方法。 - 前記蓄積キャパシタは、
前記導電性ソース/ドレイン層の前記平面上部表面に隣接し、それに電気的に接続されている、第1の電極層と、
該第1の電極層に隣接する誘電体層と、
該誘電体層に隣接する第2の電極層と、
を含む請求項6記載の集積回路メモリ装置の製造方法。 - 垂直方向に前記基板に隣接し横方向に前記ピラーに隣接する、少なくとも1つの下部誘電体層と、
垂直方向に該少なくとも1つの下部誘電体層の上方に間隔を空けて配置され、横方向に前記ピラーに隣接する、少なくとも1つの上部誘電体層とを含み、
前記ゲートは前記少なくとも一つの下部誘電体層と前記上部誘電体層の間にあることを特徴とする請求項6記載の集積回路メモリ装置の製造方法。 - 前記ゲートは、チャネル領域に近接する前記ピラーの互いに対向する表面上に配置された第1のゲートと第2のゲートからなることを特徴とする請求項8記載の集積回路メモリ装置の製造方法。
- 前記少なくとも一つの上部誘電体層が、前記ゲート上の酸化物層及び前記酸化物層上の窒化物層を含むことを特徴とする請求項8記載の集積回路メモリ装置の製造方法。
Applications Claiming Priority (2)
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US09/553868 | 2000-04-20 | ||
US09/553,868 US6603168B1 (en) | 2000-04-20 | 2000-04-20 | Vertical DRAM device with channel access transistor and stacked storage capacitor and associated method |
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JP2001122417A Division JP2001308203A (ja) | 2000-04-20 | 2001-04-20 | チャネルアクセストランジスタおよび積層型蓄積キャパシタを備えた垂直dram装置および関連方法 |
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JP2008047933A JP2008047933A (ja) | 2008-02-28 |
JP4888975B2 true JP4888975B2 (ja) | 2012-02-29 |
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JP2001122417A Pending JP2001308203A (ja) | 2000-04-20 | 2001-04-20 | チャネルアクセストランジスタおよび積層型蓄積キャパシタを備えた垂直dram装置および関連方法 |
JP2007241699A Expired - Fee Related JP4888975B2 (ja) | 2000-04-20 | 2007-09-19 | チャネルアクセストランジスタおよび積層型蓄積キャパシタを備えた垂直dram装置および関連方法 |
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Country | Link |
---|---|
US (1) | US6603168B1 (ja) |
EP (1) | EP1148552A3 (ja) |
JP (2) | JP2001308203A (ja) |
KR (1) | KR100757697B1 (ja) |
TW (1) | TW490840B (ja) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6706603B2 (en) * | 2001-02-23 | 2004-03-16 | Agere Systems Inc. | Method of forming a semiconductor device |
US6478231B1 (en) * | 2001-06-29 | 2002-11-12 | Hewlett Packard Company | Methods for reducing the number of interconnects to the PIRM memory module |
US20030052365A1 (en) * | 2001-09-18 | 2003-03-20 | Samir Chaudhry | Structure and fabrication method for capacitors integratible with vertical replacement gate transistors |
US7372091B2 (en) * | 2004-01-27 | 2008-05-13 | Micron Technology, Inc. | Selective epitaxy vertical integrated circuit components |
JP4164452B2 (ja) * | 2004-02-02 | 2008-10-15 | キヤノン株式会社 | 情報処理方法及び装置 |
US7504685B2 (en) * | 2005-06-28 | 2009-03-17 | Micron Technology, Inc. | Oxide epitaxial isolation |
JP5525156B2 (ja) * | 2008-12-09 | 2014-06-18 | ピーエスフォー ルクスコ エスエイアールエル | 半導体装置、および該半導体装置の製造方法 |
JP4530098B1 (ja) | 2009-05-29 | 2010-08-25 | 日本ユニサンティスエレクトロニクス株式会社 | 半導体装置 |
US9177872B2 (en) | 2011-09-16 | 2015-11-03 | Micron Technology, Inc. | Memory cells, semiconductor devices, systems including such cells, and methods of fabrication |
KR20230104756A (ko) * | 2012-05-10 | 2023-07-10 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 |
US9698261B2 (en) | 2014-06-30 | 2017-07-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Vertical device architecture |
US9911848B2 (en) * | 2014-08-29 | 2018-03-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Vertical transistor and method of manufacturing the same |
CN118235532A (zh) * | 2021-11-09 | 2024-06-21 | 新加坡优尼山帝斯电子私人有限公司 | 半导体内存装置及半导体内存装置的制造方法 |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4554570A (en) * | 1982-06-24 | 1985-11-19 | Rca Corporation | Vertically integrated IGFET device |
JPH0793365B2 (ja) * | 1984-09-11 | 1995-10-09 | 株式会社東芝 | 半導体記憶装置およびその製造方法 |
US5140389A (en) | 1988-01-08 | 1992-08-18 | Hitachi, Ltd. | Semiconductor memory device having stacked capacitor cells |
JP2941039B2 (ja) * | 1990-11-08 | 1999-08-25 | 沖電気工業株式会社 | 半導体メモリ装置の製造方法 |
JPH04188869A (ja) * | 1990-11-22 | 1992-07-07 | Mitsubishi Electric Corp | 接合型電界効果トランジスタとキャパシタとを含む半導体記憶装置およびその製造方法 |
KR940000513B1 (ko) * | 1991-08-21 | 1994-01-21 | 현대전자산업 주식회사 | Dram셀 및 그 제조방법 |
US5208172A (en) * | 1992-03-02 | 1993-05-04 | Motorola, Inc. | Method for forming a raised vertical transistor |
US5234856A (en) | 1992-04-15 | 1993-08-10 | Micron Technology, Inc. | Dynamic random access memory cell having a stacked-trench capacitor that is resistant to alpha particle generated soft errors, and method of manufacturing same |
US5335138A (en) | 1993-02-12 | 1994-08-02 | Micron Semiconductor, Inc. | High dielectric constant capacitor and method of manufacture |
JPH06260610A (ja) * | 1993-03-02 | 1994-09-16 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
JP3403231B2 (ja) * | 1993-05-12 | 2003-05-06 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
JP3197134B2 (ja) * | 1994-01-18 | 2001-08-13 | 株式会社東芝 | 半導体装置 |
KR0135803B1 (ko) | 1994-05-13 | 1998-04-24 | 김광호 | 상.하로 분리된 커패시터를 갖는 반도체 메모리장치 및 그 제조방법 |
JP3745392B2 (ja) * | 1994-05-26 | 2006-02-15 | 株式会社ルネサステクノロジ | 半導体装置 |
US5885882A (en) | 1995-07-18 | 1999-03-23 | Micron Technology, Inc. | Method for making polysilicon electrode with increased surface area making same |
US5668036A (en) | 1996-06-21 | 1997-09-16 | Vanguard International Semiconductor Corporation | Fabrication method of the post structure of the cell for high density DRAM |
US5712813A (en) | 1996-10-17 | 1998-01-27 | Zhang; Guobiao | Multi-level storage capacitor structure with improved memory density |
KR19980028402A (ko) * | 1996-10-22 | 1998-07-15 | 문정환 | 디램(dram) 셀의 구조 및 그 제조 방법 |
US5885864A (en) | 1996-10-24 | 1999-03-23 | Micron Technology, Inc. | Method for forming compact memory cell using vertical devices |
US5824582A (en) | 1997-06-04 | 1998-10-20 | Vanguard International Semiconductor Corporation | Stack DRAM cell manufacturing process with high capacitance capacitor |
US5909618A (en) | 1997-07-08 | 1999-06-01 | Micron Technology, Inc. | Method of making memory cell with vertical transistor and buried word and body lines |
US6078072A (en) * | 1997-10-01 | 2000-06-20 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having a capacitor |
US6027975A (en) | 1998-08-28 | 2000-02-22 | Lucent Technologies Inc. | Process for fabricating vertical transistors |
-
2000
- 2000-04-20 US US09/553,868 patent/US6603168B1/en not_active Expired - Lifetime
-
2001
- 2001-04-19 KR KR1020010021021A patent/KR100757697B1/ko not_active IP Right Cessation
- 2001-04-19 TW TW090109388A patent/TW490840B/zh not_active IP Right Cessation
- 2001-04-20 EP EP01303617A patent/EP1148552A3/en not_active Withdrawn
- 2001-04-20 JP JP2001122417A patent/JP2001308203A/ja active Pending
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2007
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Also Published As
Publication number | Publication date |
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US6603168B1 (en) | 2003-08-05 |
EP1148552A3 (en) | 2005-10-12 |
KR20010098730A (ko) | 2001-11-08 |
JP2001308203A (ja) | 2001-11-02 |
EP1148552A2 (en) | 2001-10-24 |
KR100757697B1 (ko) | 2007-09-13 |
JP2008047933A (ja) | 2008-02-28 |
TW490840B (en) | 2002-06-11 |
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