410440 五、發明說明（1) 本發明係％關於半導體記憶元件的製造方法，特別是 有關於一種動態隨機存取記憶單元（dynamic random a c c e s s m e m o r y，D Ιί A Μ)之電容之製造方法。 動態隨機存取記憶體為一廣泛應用的積體電路元件， 特別在現今的資訊電子產業中更有不可或缺的地位。隨著 技術的演進，目前生產線上常見的DRAM記憶單元大多是由 一電晶體T和一電容C所構成’如第1圖的電路示意圖所示 。電晶體T的汲極（drain)係連接到一對應的位元線（bi t 1 i ne，BL)，和源極（source )連接到一電容C的下電極 - (bottom electrode)，而閘極（gate)則連接到一對應的字 元線（word line, WL)，電容C 的上電極（top electrode) ^ 係連接到一固定電壓源（例如接地），而在下電極和上電極 間隔著一介電層。 電容C是用來健存電子資訊的，其應具備足夠大的電： 容量，以避免資料的流失並減低充電更新（refresh)的頻， 率。一般可由兩個方向著手來增加電容C的電容量，一為 減少介電層的厚度，一為增加下電極的表面積。在減少介 電層的厚度方面，現今製造的電容均已使用極薄的介電層 ’然而其厚度並非無限制的縮小，當介電層的厚度小於5 〇 埃時’極可能因為直接載子隨穿（direct carrier 、 tunneling)而產生過大的漏電流，影響元件的性質。因此 目前許多研發都致力於增加下電極的表面積，藉以提升電 - 容的電容量。 在傳統少於一百萬位元（1MB)的DRAM製程中，一般多410440 V. Description of the invention (1) The present invention relates to a method for manufacturing a semiconductor memory element, and more particularly to a method for manufacturing a capacitor of a dynamic random access memory cell (dynamic random a c c s s m m m r r y, D Ι A Μ). Dynamic random access memory is a widely used integrated circuit component, especially in today's information electronics industry. With the evolution of technology, the common DRAM memory cells on the current production line are mostly composed of a transistor T and a capacitor C ', as shown in the circuit diagram in FIG. 1. The drain of transistor T is connected to a corresponding bit line (bi t 1 ne, BL), and the source is connected to the bottom electrode of a capacitor C (bottom electrode), and the gate The gate is connected to a corresponding word line (WL). The top electrode of the capacitor C is connected to a fixed voltage source (such as ground), and the lower electrode and the upper electrode are spaced apart. A dielectric layer. Capacitor C is used to store electronic information, and it should have enough electricity: capacity to avoid data loss and reduce the frequency and rate of refresh. Generally, the capacitance of the capacitor C can be increased in two directions, one is to reduce the thickness of the dielectric layer, and the other is to increase the surface area of the lower electrode. In terms of reducing the thickness of the dielectric layer, extremely thin dielectric layers have been used in capacitors manufactured today. However, its thickness is not reduced indefinitely. When the thickness of the dielectric layer is less than 50 angstroms, it is most likely due to direct carriers. Excessive leakage current is generated with direct carrier (tunneling), which affects the properties of the device. Therefore, many current R & D efforts are focused on increasing the surface area of the lower electrode, thereby increasing the capacitance of the capacitor. In traditional DRAM processes with less than one million bits (1MB), there are usually many
410440 五、發明說明（2) 利用二度空間的電容來儲存資料，亦即泛稱的平面型電$ (planar-type capacitor)。然而，平面型電容需利用基 底一相當大的面積來形成下電極，才可提供足夠的電容4 ，所以並不適用於目前曰益高度積秦化之DRAM 元件的製 程要求。 通常，高度積集化的DRAM需要利用三度空間的電容结 構，例如堆疊型（stack type)的電容記憶元件。而在各種 堆疊型電容的記憶元件中，電極具有向上突出部分的冠狀 、 電容（crown type capacitor)構造’由於其内外側表面均-可提供有效的電容面積，相當適合於製造高度積集化的元 件，特別是大於64MB位元的記憶元件。所以許多技術均係⑩ 針對此一形式的冠狀電容進行改艮’以達到在元件尺寸縮 小時仍可以確保提供足夠大之電容量之目的。 而習知之冠狀電容的製造方法’大多製成圓桎狀 ， (cylin dr i cal)或鰭狀（fin)電容。然而圓柱狀電容之向j 突出部分的高度並不能太高否則會有結構不穩之顧慮；而 鰭狀（f i η)電容雖可提供較大之表面積，但卻會面臨到轄 狀構造易崩塌之問題。因此上述雨類習知電容皆因其結構 不夠穩定性’而使電容量不易大幅提高。 因此’本發明之目的在提供〆種動態隨機存取記憶單 元之製造方法，使所製出之電容能具有較穩定之結構並可 提昇電容量。 根攄上述目的’本發明提出〆種動態隨機存取記恢單 元之電容的製造方法，適用於一具有開關元件之半導體基410440 V. Description of the invention (2) Use two-degree space capacitors to store data, which is generally referred to as a planar-type capacitor (planar-type capacitor). However, planar capacitors need to use a relatively large area of the substrate to form the lower electrode in order to provide sufficient capacitance4, so they are not suitable for the current process requirements of highly integrated DRAM components. Generally, highly integrated DRAM requires a three-dimensional space capacitor structure, such as a stack type capacitor memory element. In the memory elements of various stacked capacitors, the electrodes have a crown-shaped, crown-type capacitor structure that protrudes upwards. Because of its internal and external surfaces, it can provide an effective capacitance area, which is quite suitable for manufacturing highly integrated capacitors. Devices, especially memory devices larger than 64 MB. Therefore, many technologies are based on the modification of this type of crown capacitor to achieve the purpose of ensuring a sufficiently large capacitance even when the component size is reduced. The conventional method for manufacturing a crown capacitor is mostly made into a cylindrical or fin capacitor. However, the height of the protruding portion of the cylindrical capacitor toward j should not be too high, otherwise there may be concerns about structural instability; while the fin-shaped (fi η) capacitor can provide a large surface area, it will face the collapse of the jurisdictional structure. Problem. Therefore, the above-mentioned conventional rain capacitors are not easy to greatly increase their capacitance due to their insufficient structural stability. Therefore, the object of the present invention is to provide a method for manufacturing a dynamic random access memory cell, so that the capacitor can have a more stable structure and can improve the capacitance. Based on the above object, the present invention proposes a method for manufacturing a capacitor of a dynamic random access memory recovery unit, which is suitable for a semiconductor substrate having a switching element.
第5頁 — 41Q44Q__ 五、發明說明（3^ --—--____ 底上製造電容’而上述製造方法包括下列步驟. 導體上形成具有連通至上述開關元件之接觸開口在上述半 ;在上述絕緣層上和上述接觸開口内形成—第—之絶緣層 藉以和上述開關元件形成電性連接；在上述第:導電層， 之對準上述接觸開口間之處形成一第一犧牲層了導電層上 二犧牲層以填滿上述第一犧牲層間之區域；^上形成〜第 第二犧牲層上依序形成一第二導電層和與第—述第一和 相同之第三犧牲層；定義上述第一、第二、第犧牷層材料 上述第一、第二導電層，以在上述絕緣層上之牧層和 觸開口處形成一堆疊結構；選擇性地移除上述^準上逑接 之部分側壁；在上述堆疊結構之側壁上形成—二犧牲層 ’而上述導電間隔物會填入被移除之上述第二播電間隔物 據之空間；以上述第二犧牲層為罩幕，非等向 ^層所佔 述導電間隔物、上述第一和第二導電層，以形 ^蝕刻上 在被移除之上述第二犧牲層所佔據之空間内；移導電柱 一、第二和第三犧牲層，留下上述第一、第二導^上述第 述導電柱’形成一侧壁有開口且中空之窗形導妹$和上 後更可在上述窗形導電結構上再形成複數個相^办’之 電結構以共同構成上述電容之上電極；以及在上述7形導 上依序形成介電層和上述電容之上電極。 電極 為了讓本發明之上述目的和特點更明顯易僅， 舉若干較佳實施例’並配合所附圖式，做詳文特 說明 說明如下： 第1圖係一般動態隨機存取記憶單元的電路土 不恩圖；Page 5 — 41Q44Q__ V. Description of the invention (3 ^ -----____ Manufacturing capacitors on the bottom 'and the above manufacturing method includes the following steps. The conductor is formed with a contact opening communicating with the switching element in the above half; the above insulation A first insulating layer is formed on the layer and inside the contact opening to form an electrical connection with the switching element; a first sacrificial layer is formed on the conductive layer at the place where the first: conductive layer is aligned between the contact openings. Two sacrificial layers are used to fill the area between the first sacrificial layers; a second conductive layer and a third sacrificial layer identical to the first and the first are sequentially formed on the second sacrificial layer; First, second, and first sacrificial layers The above first and second conductive layers are used to form a stacked structure on the insulating layer and the contact openings on the above-mentioned insulating layer; the above-mentioned quasi-upper part is selectively removed. Side wall; two sacrificial layers are formed on the side wall of the above-mentioned stacked structure, and the conductive spacers will fill the space of the above-mentioned second broadcast spacer; the above-mentioned second sacrificial layer is used as a cover, and is non-isotropic ^ Layer The occupied conductive spacers, the first and second conductive layers are etched in the shape of the space occupied by the removed second sacrificial layer; the first, second, and third sacrificial layers of the conductive pillar are moved, The above-mentioned first and second conductive pillars are left behind, and the above-mentioned first conductive pillars are formed into a hollow window-shaped guide with openings on the side walls, and the upper and lower sides can further form a plurality of phases on the window-shaped conductive structure. The electrical structure together constitutes the above-mentioned capacitor upper electrode; and a dielectric layer and the above-mentioned capacitor upper electrode are sequentially formed on the 7-shaped guide. In order to make the above-mentioned objects and features of the present invention more obvious and easy, for example, The preferred embodiment is described in detail with the accompanying drawings, as follows: Figure 1 is a circuit diagram of a general dynamic random access memory unit;
第6頁 五、發明說明（4) 第2至第4圖、第6至第9圖均為剖面示意圖’用以說明 依據本發明的一較佳實施例的製造流程。 第5圖為頂部透視圖，用以說明以一選擇性钱刻程序 處理堆疊結構之結果。 第1 0圖為剖面示意圖，用以說明堆疊板數個囪形導電 結構的結果。 符號說明 0 1 0〜基底；1 2 -場氧化層；G ~閘極構造；2 0 ~閘極間隔物； 22〜源極/汲極區；24〜絕緣層；26〜接觸開口； 28〜第一導 電層；30〜第一犧牲層；32 ;第二犧牲層；34〜第二導電層 ;36〜第三犧牲層；37~堆疊結構；38〜導電間隔物；38’ ~ 導電柱；以及40〜窗形導電結構。 實施例 本發明所述之動態隨機存取記憶單元之電容之製造方 法可施行於一記憶體元件上，例如使用具N通道之金屬氧 化半導體場效電晶體（M0SFET)為開關元件之DRAM元件。然 而，本發明所描述之動態隨機存取記憶單元之電容之製造 方法也可施行於具P通道的MOSFET元件。Page 6 V. Description of the invention (4) Figures 2 to 4 and 6 to 9 are schematic sectional views' used to explain the manufacturing process according to a preferred embodiment of the present invention. Figure 5 is a top perspective view illustrating the results of processing a stacked structure with a selective coining process. Fig. 10 is a schematic cross-sectional view for explaining the results of several stack-shaped conductive structures of the stacked plates. Explanation of symbols 0 1 0 ~ substrate; 1 2 -field oxide layer; G ~ gate structure; 20 ~ gate spacer; 22 ~ source / drain region; 24 ~ insulating layer; 26 ~ contact opening; 28 ~ First conductive layer; 30 to first sacrificial layer; 32; second sacrificial layer; 34 to second conductive layer; 36 to third sacrificial layer; 37 to stacked structure; 38 to conductive spacer; 38 'to conductive pillar; And 40 ~ window-shaped conductive structure. Example The method for manufacturing a capacitor of a dynamic random access memory cell according to the present invention can be implemented on a memory element, such as a DRAM element using an N-channel metal oxide semiconductor field effect transistor (MOSFET) as a switching element. However, the method for manufacturing a capacitor of a dynamic random access memory cell described in the present invention can also be applied to a P-channel MOSFET device.
請參見第2圖，其顯示本發明之起始步驟。先提供一 半導體基底10，在此以一晶格方位為<1〇〇>2Ρ型矽基底為 例。在基底1 0上以一熱氧化製程，如局部氧化法（LOC0S) 形成一場氧化層1 2以界定出將形成記憶單元的元件區 (active area)。接著依序沈積一閘氧化層14、一複晶矽 層1 6、一石夕化鎢層（ffS ix) 1 8後’用微影技術和非等向性蝕 410440 五、發明說明¢5) ，程序對上述各層餘刻圖案’以形成一問極構造g。接著 極構造G旁形成—淡掺雜的源極/没極區，例如以間極 冓wG為罩幕，離子植入如磷或砷型摻質進入半導體基 底1 〇而形成。然後在閘極構造G的侧壁上形成一間隔物 (spacer)20，例如沈積及非等向性地回蝕一絕緣層而形成 間隔物2 0。之後形成濃摻雜的源極/汲極區，完成源極/汲 極區22之製造。例如以間隔物2〇為罩幕，離子植入較高濃 度的之N型摻源，如磷或砷，進入半導體基底丨〇。至此， 完成一電晶體元件的製造。 接著在上述包含電晶體元件的基底1〇上沈積至少一層\ 絕巧層，以隔離電晶體與後續形成之導電層，及提供利於γ 後續製程之平坦表面，並可依不同的元件設計製作必須的 導線於其間。例如在基底丨〇上形成一絕緣層24後，再以如 化學機械研磨法CMP技術平坦化絕緣層2 4 ^絕緣層2 4之材-料可以是硼磷矽玻璃、磷矽玻璃、硼矽玻璃或氧化矽。 然後以微影技術和蝕刻程序在絕緣層24中形成一接觸 開口 2 6 ’以露出電晶體之源極/没極區2 2之一。接著在上 述接觸開口 26内和上述絕緣層24表面上形成一第一導電 層28。第一導電層28由摻雜之複晶矽構成且厚度介於約 1 50 0至3000埃之間較佳。 ' 然後請參見第3圖’顯示依序形成第一犧牲層3 〇和第 二犧牲結層32在第一導電層28上之結果。包括下列步驟： 在第一導電層28上形成一第一犧牲材料後’定義第一犧牲 材料以在對準上述接觸開口 26處形成一第一犧牲層3〇。之 410440 五、發明說明（6) 後採用與第一犧牲層㈣+同之材料形《第二犧牲材 順應性地覆蓋在第一犧牲層30和第一導電層28上後，以 坦化步驟，如化學機械研磨法（CMp)或回蝕第二犧牲材 至第一犧牲層30之頂端表面，形成第二犧牲層32。第— 牲層30之材料為氮氧化矽（Si〇xNj且厚度介於約ι〇㈣至 1 50 00埃之間較佳，而第二犧牲層32之材料為硼磷矽破 且厚度介於約1 〇 〇 〇至1 5 〇 0 〇埃之間較佳。 ,接著請參見第4圖。在第一和第二犧牲層3〇和32上依 序形成第二導電層34和與第一犧牲層3〇材料相同之第三Please refer to Fig. 2, which shows the initial steps of the present invention. First, a semiconductor substrate 10 is provided. Here, a lattice orientation is < 100 > 2P-type silicon substrate as an example. An oxide layer 12 is formed on the substrate 10 by a thermal oxidation process, such as a local oxidation method (LOCOS), so as to define an active area of a memory cell. Then sequentially deposit a gate oxide layer 14, a polycrystalline silicon layer 16 and a stone tungsten oxide layer (ffS ix) 18 after 'using lithography technology and anisotropic etching 410440 5. Description of the invention ¢ 5), The program patterned the above layers to form an interrogation structure g. Next, it is formed next to the electrode structure G—a lightly doped source / electrode region, for example, an interelectrode 冓 wG is used as a mask, and an ion implantation such as a phosphorus or arsenic type dopant is formed into the semiconductor substrate 10. A spacer 20 is then formed on the sidewall of the gate structure G, such as deposition and anisotropically etch back an insulating layer to form the spacer 20. A heavily doped source / drain region is then formed to complete the fabrication of the source / drain region 22. For example, a spacer 20 is used as a mask, and a higher-concentration N-type dopant such as phosphorus or arsenic is implanted into the semiconductor substrate. So far, the manufacture of a transistor element is completed. Then deposit at least one layer on the substrate 10 including the transistor element to isolate the transistor from the subsequent conductive layer, and provide a flat surface that is conducive to the subsequent process of γ. It can be manufactured according to different element designs. In between. For example, after an insulating layer 24 is formed on the substrate, the insulating layer 2 4 is planarized by a CMP technique such as chemical mechanical polishing. The material of the insulating layer 24 can be borophosphosilicate glass, phosphosilicate glass, borosilicate Glass or silicon oxide. Then, a lithography technique and an etching process are used to form a contact opening 26 'in the insulating layer 24 to expose one of the source / non-electrode regions 22 of the transistor. A first conductive layer 28 is then formed in the contact opening 26 and on the surface of the insulating layer 24. The first conductive layer 28 is made of doped polycrystalline silicon and preferably has a thickness between about 150 and 3000 angstroms. 'Then refer to FIG. 3' to show the result of sequentially forming the first sacrificial layer 30 and the second sacrificial junction layer 32 on the first conductive layer 28. The method includes the following steps: After forming a first sacrificial material on the first conductive layer 28, the first sacrificial material is defined to form a first sacrificial layer 30 at the contact opening 26. No. 410440 V. Description of the invention (6) The same material shape as that of the first sacrificial layer ㈣ + is used. After the second sacrificial material conformably covers the first sacrificial layer 30 and the first conductive layer 28, a frank step For example, chemical mechanical polishing (CMp) or etching back the second sacrificial material to the top surface of the first sacrificial layer 30 to form the second sacrificial layer 32. The first- animal layer 30 is made of silicon oxynitride (SiOxNj and a thickness between about ι0㈣ and 1500 Angstroms is preferred, and the material of the second sacrificial layer 32 is borophosphosilicate broken and the thickness is between It is preferably between about 1000 and 15,000 Angstroms. Next, please refer to FIG. 4. A second conductive layer 34 and a first conductive layer 34 are sequentially formed on the first and second sacrificial layers 30 and 32. Sacrificial layer 30 is the same as the third material
II 牲層36，如以氮氧化矽形成較佳，而第二導電層^由摻雜 之複晶石夕構成較佳。 之後可以微影製程及蝕刻步騍定義第一、第二導電層 28、34及第一、第二、第三犧牲層3〇、以，以在絕緣； 24上之對準接觸開口 26處形成一堆疊結構37。 ‘ 然後進行本發明之重要步驟。以一選擇性蝕刻程序處 理上述堆疊結構3?，其中該姓刻程序對第二犧牲層32之敍 刻選擇性係大於第—、第三犧牲層3〇、36以及第一、第二 導電層28、34，因此第二犧牲層32被去除之部分較堆疊結 構37之其他部分為多。例如：若第一、第三犧牲層3〇、36 皆為氮氧化矽，第二犧牲層32為硼磷矽玻璃，而第一和第 一導電層28和34皆為複晶矽的話，可選擇以氫氟酸為蝕刻 反應物來進行濕式蝕刻程序。第5圖係此結果之頂部透視 圖，標,32係表示部分第二犧牲層32被去除而留下之空 間。而第6圖及以後之圖示皆為沿卜丨，線（第5圖）作一橫切The second layer 36 is preferably formed of silicon oxynitride, and the second conductive layer ^ is preferably composed of doped polycrystalline spar. After that, the lithography process and etching steps can be performed to define the first and second conductive layers 28, 34 and the first, second, and third sacrificial layers 30 to form an insulation; 24 is formed at the alignment contact openings 26 One stacked structure 37. ‘Then proceed with the important steps of the invention. A selective etching process is used to process the above-mentioned stacked structure 3 ?, wherein the engraving selectivity of the second sacrificial layer 32 to the second sacrificial layer 32 is greater than that of the first, third sacrificial layers 30, 36, and the first and second conductive layers 28, 34, so more portions of the second sacrificial layer 32 are removed than other portions of the stacked structure 37. For example, if the first and third sacrificial layers 30 and 36 are both silicon oxynitride, the second sacrificial layer 32 is borophosphosilicate glass, and the first and first conductive layers 28 and 34 are both polycrystalline silicon, then Hydrofluoric acid was selected as the etching reactant for the wet etching process. FIG. 5 is a top perspective view of the result, and the reference numeral 32 indicates a space left by a portion of the second sacrificial layer 32 being removed. The diagrams in Figure 6 and later are cut along the line (Figure 5).
[ _410440_ 五、發明說明C8) 容量，所以可達到下一世代之高記憶體及有效之空間利用 的需求。同時，熟知此技藝者應可瞭解，本發明可用之物 質材料並不限於實施例中所引述者，其能由各種恰當特性 之物質和形成方法所置換，並且本發明之結構空間亦不限 於實施例所引用之尺寸大小。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。[_410440_ V. Description of the invention C8) Capacity, so it can meet the needs of the next generation of high memory and effective space utilization. At the same time, those skilled in the art should understand that the material materials usable in the present invention are not limited to those cited in the examples, they can be replaced by various appropriate characteristics of materials and forming methods, and the structural space of the present invention is not limited to implementation. The size of the example. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.
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