JP4725817B2 - 複合基板の製造方法 - Google Patents

複合基板の製造方法 Download PDF

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Publication number
JP4725817B2
JP4725817B2 JP2008515459A JP2008515459A JP4725817B2 JP 4725817 B2 JP4725817 B2 JP 4725817B2 JP 2008515459 A JP2008515459 A JP 2008515459A JP 2008515459 A JP2008515459 A JP 2008515459A JP 4725817 B2 JP4725817 B2 JP 4725817B2
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piece
substrate
substrate body
main surface
composite
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Japanese (ja)
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JPWO2007132612A1 (ja
Inventor
範夫 酒井
幸男 山本
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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    • H—ELECTRICITY
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    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Combinations Of Printed Boards (AREA)
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JP2008515459A 2006-05-17 2007-04-13 複合基板の製造方法 Expired - Fee Related JP4725817B2 (ja)

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JP5481680B2 (ja) 2010-04-28 2014-04-23 三菱電機株式会社 半導体装置および半導体装置の製造方法
JP2012147403A (ja) * 2011-01-14 2012-08-02 Mitsumi Electric Co Ltd 高周波モジュール
JP2013069800A (ja) * 2011-09-21 2013-04-18 Nec Corp 半導体装置の実装構造及び実装方法
WO2013054808A1 (fr) * 2011-10-14 2013-04-18 株式会社村田製作所 Substrat multicouche et module muni d'un substrat multicouche
CN104471707B (zh) * 2012-07-26 2017-07-04 株式会社村田制作所 半导体模块
JP7167945B2 (ja) * 2018-01-11 2022-11-09 株式会社村田製作所 部品内蔵モジュールおよびその製造方法
WO2020218289A1 (fr) * 2019-04-26 2020-10-29 株式会社村田製作所 Composant de module, module d'antenne et dispositif de communication

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01204379A (ja) * 1987-12-08 1989-08-16 Rogers Corp リード無しセラミックチップキャリヤ用ソケット
JPH02207559A (ja) * 1989-02-07 1990-08-17 Fujitsu Ltd 二列並行多端子型混成集積回路装置
JPH0742164U (ja) * 1993-12-24 1995-07-21 富士通テン株式会社 電子部品実装回路基板
JPH07249733A (ja) * 1994-03-14 1995-09-26 Fujitsu Ltd 半導体装置
JPH11121897A (ja) * 1997-10-14 1999-04-30 Fujitsu Ltd 複数の回路素子を基板上に搭載するプリント配線基板の製造方法及びプリント配線基板の構造
JP2003068968A (ja) * 2001-08-29 2003-03-07 Pfu Ltd 半導体集積回路装置
WO2006027888A1 (fr) * 2004-09-08 2006-03-16 Murata Manufacturing Co., Ltd. Substrat de céramique composite

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01204379A (ja) * 1987-12-08 1989-08-16 Rogers Corp リード無しセラミックチップキャリヤ用ソケット
JPH02207559A (ja) * 1989-02-07 1990-08-17 Fujitsu Ltd 二列並行多端子型混成集積回路装置
JPH0742164U (ja) * 1993-12-24 1995-07-21 富士通テン株式会社 電子部品実装回路基板
JPH07249733A (ja) * 1994-03-14 1995-09-26 Fujitsu Ltd 半導体装置
JPH11121897A (ja) * 1997-10-14 1999-04-30 Fujitsu Ltd 複数の回路素子を基板上に搭載するプリント配線基板の製造方法及びプリント配線基板の構造
JP2003068968A (ja) * 2001-08-29 2003-03-07 Pfu Ltd 半導体集積回路装置
WO2006027888A1 (fr) * 2004-09-08 2006-03-16 Murata Manufacturing Co., Ltd. Substrat de céramique composite

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