JPWO2007132612A1 - 複合基板及びその製造方法 - Google Patents
複合基板及びその製造方法 Download PDFInfo
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Abstract
Description
10 基板本体
10a 一方主面
20,22 チップ状電子部品
24 樹脂層
26,27,28 チップ状電子部品
30 接続部材
32 第1片
34 中間片
36 第2片
Claims (14)
- 基板本体の一方主面に、金属薄板の折り曲げ加工により形成され中間片の両端にそれぞれ第1片と第2片とが連続する複数の接続部材のそれぞれの前記第1片を接合するとともに、前記基板本体の前記一方主面にチップ状電子部品を搭載する、第1の工程と、
前記チップ状電子部品の少なくとも一部と少なくとも前記接続部材のそれぞれの前記第1片とを覆い、かつ、少なくとも前記接続部材のそれぞれの前記第2片の前記基板本体とは反対側の面が露出するように、前記基板本体の前記一方主面に樹脂層を形成する、第2の工程と、
を備えることを特徴とする複合基板の製造方法。 - 前記第2の工程において、前記チップ状電子部品の少なくとも一部と少なくとも前記接続部材のそれぞれの前記第1片とを覆い、かつ、少なくとも前記接続部材のそれぞれの前記第2片の前記基板本体とは反対側の面が露出するように、前記基板本体の前記一方主面に液状の樹脂を塗布し、硬化させることにより、前記樹脂層を形成することを特徴とする、請求項1に記載の複合基板の製造方法。
- 前記第1の工程と前記第2の工程とを、複数個分の前記基板本体となる部分を含む集合基板の状態で、複数個分の前記複合基板についてまとめて行い、
前記第2の工程の後に、前記複合基板の分割線に沿って前記樹脂層にスリットを形成する工程を、さらに備えることを特徴とする、請求項1又は2に記載の複合基板の製造方法。 - 前記基板本体の他方主面に他のチップ状電子部品を搭載する工程を、さらに備えることを特徴とする、請求項1、2、又は3に記載の複合基板の製造方法。
- 前記基板本体は、1050℃以下で焼結する複数のセラミック層を積層してなる積層体の内部に導体パターンを有するセラミック多層基板であることを特徴とする、請求項1〜4のいずれか一項に記載の複合基板の製造方法。
- 前記第1の工程において、前記接続部材は、
前記第1片及び前記第2片が前記中間片に関して同じ側に延在し、
前記中間片同士が対向し、かつ、前記第1片及び前記第2片が前記中間片同士の間よりも外側に延在するように、前記第1片が前記基板本体の前記一方主面に接合されることを特徴とする、請求項1〜5のいずれか一項に記載の複合基板の製造方法。 - 前記第1の工程において、前記接続部材は
前記第1片及び前記第2片が前記中間片に関して互いに反対側に延在し、
前記中間片同士が対向し、かつ、前記第1片又は前記第2片の一方同士が前記中間片同士の間よりも外側に延在し、かつ、前記第1片又は前記第2片の他方同士が前記中間片同士の間に延在するように、前記第1片が前記基板本体の前記一方主面に接合されることを特徴とする、請求項1〜5のいずれか一項に記載の複合基板の製造方法。 - 前記接続部材は、前記第1片の面積が、前記第2片の面積よりも大きいことを特徴とする、請求項1〜7のいずれか一項に記載の複合基板の製造方法。
- 基板本体と、
金属薄板の折り曲げ加工により形成され、中間片の両端にそれぞれ第1片と第2片とが連続し、前記第1片が前記基板本体の一方主面に接合された複数の接続部材と、
前記基板本体の前記一方主面に搭載されたチップ状電子部品と、
前記チップ状電子部品と少なくとも前記接続部材のそれぞれの前記第1片とを覆い、かつ、少なくとも前記接続部材のそれぞれの前記第2片の前記基板本体とは反対側の面が露出するように、前記基板本体の前記一方主面全体に同一樹脂材料で形成された樹脂層と、
を備えることを特徴とする複合基板。 - 前記基板本体の他方主面に搭載された他のチップ状電子部品を、さらに備えることを特徴とする、請求項9に記載の複合基板。
- 前記基板本体は、1050℃以下で焼結する複数のセラミック層を積層してなる積層体の内部に導体パターンを有するセラミック多層基板であることを特徴とする、請求項9又は10に記載の複合基板。
- 前記接続部材は、
前記第1片及び前記第2片が前記中間片に関して同じ側に延在し、
前記中間片同士が対向し、かつ、前記第1片及び前記第2片が前記中間片同士の間よりも外側に延在することを特徴とする、請求項9、10又は11に記載の複合基板。 - 前記接続部材は、
前記第1片及び前記第2片が前記中間片に関して互いに反対側に延在し、
前記中間片同士が対向し、かつ、前記第1片又は前記第2片の一方同士が前記中間片同士の間よりも外側に延在し、かつ、前記第1片又は前記第2片の他方同士が前記中間片同士の間に延在するように、前記第1片が前記基板本体の前記一方主面に接合されることを特徴とする、請求項9、10又は11に記載の複合基板。 - 前記接続部材は、前記第1片の面積が、前記第2片の面積よりも大きいことを特徴とする、請求項9〜13のいずれか一項に記載の複合基板。
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JPH01204379A (ja) * | 1987-12-08 | 1989-08-16 | Rogers Corp | リード無しセラミックチップキャリヤ用ソケット |
JPH02207559A (ja) * | 1989-02-07 | 1990-08-17 | Fujitsu Ltd | 二列並行多端子型混成集積回路装置 |
JPH0742164U (ja) * | 1993-12-24 | 1995-07-21 | 富士通テン株式会社 | 電子部品実装回路基板 |
JPH07249733A (ja) * | 1994-03-14 | 1995-09-26 | Fujitsu Ltd | 半導体装置 |
JPH11121897A (ja) * | 1997-10-14 | 1999-04-30 | Fujitsu Ltd | 複数の回路素子を基板上に搭載するプリント配線基板の製造方法及びプリント配線基板の構造 |
JP2003068968A (ja) * | 2001-08-29 | 2003-03-07 | Pfu Ltd | 半導体集積回路装置 |
WO2006027888A1 (ja) * | 2004-09-08 | 2006-03-16 | Murata Manufacturing Co., Ltd. | 複合セラミック基板 |
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JPH01204379A (ja) * | 1987-12-08 | 1989-08-16 | Rogers Corp | リード無しセラミックチップキャリヤ用ソケット |
JPH02207559A (ja) * | 1989-02-07 | 1990-08-17 | Fujitsu Ltd | 二列並行多端子型混成集積回路装置 |
JPH0742164U (ja) * | 1993-12-24 | 1995-07-21 | 富士通テン株式会社 | 電子部品実装回路基板 |
JPH07249733A (ja) * | 1994-03-14 | 1995-09-26 | Fujitsu Ltd | 半導体装置 |
JPH11121897A (ja) * | 1997-10-14 | 1999-04-30 | Fujitsu Ltd | 複数の回路素子を基板上に搭載するプリント配線基板の製造方法及びプリント配線基板の構造 |
JP2003068968A (ja) * | 2001-08-29 | 2003-03-07 | Pfu Ltd | 半導体集積回路装置 |
WO2006027888A1 (ja) * | 2004-09-08 | 2006-03-16 | Murata Manufacturing Co., Ltd. | 複合セラミック基板 |
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