JP4700681B2 - Si回路ダイ、Si回路ダイを製作する方法およびSi回路ダイをヒートシンクに取り付ける方法並びに回路パッケージと電力モジュール - Google Patents
Si回路ダイ、Si回路ダイを製作する方法およびSi回路ダイをヒートシンクに取り付ける方法並びに回路パッケージと電力モジュール Download PDFInfo
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- JP4700681B2 JP4700681B2 JP2007502765A JP2007502765A JP4700681B2 JP 4700681 B2 JP4700681 B2 JP 4700681B2 JP 2007502765 A JP2007502765 A JP 2007502765A JP 2007502765 A JP2007502765 A JP 2007502765A JP 4700681 B2 JP4700681 B2 JP 4700681B2
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Description
US2004/0029304 A1は、複数の能動光電子デバイスを共通の基板の上に細かいピッチと高い精度でフリップチップ結合することが必要なハイブリッド光電子回路を組み立てるための費用効果のある方法を開示している。
上述の開示は共に小型の光デバイスに関するもので、接着の弱さまたははがれなど、大型のSiデバイスで起こる問題に関する方法を記述または開示していない。
この点に関する本発明の特定の目的は、集積回路ダイをCu、CuZr、CPC、またはPCMフランジに取り付けるためのはんだとしてAuSnを用いることを可能にする装置および方法を提供することである。
更に本発明の別の目的は、耐食性も持つCOB技術を用いて集積回路パッケージ、電力モジュール、または電力増幅器のフランジに集積回路ダイを取り付けるときに空隙が形成されにくくする装置および方法を提供することである。
更に本発明の別の目的は、より高い熱伝導度および電気伝導度を有するフランジを用いる可能性を与える装置および方法を提供することである。
更に本発明の別の目的は、より薄い集積回路ダイを用いる可能性を与えることにより熱伝導度および電気伝導度を良くし、これによりデバイスの信頼性と性能を高める装置および方法を提供することである。
更に本発明の別の目的は、ダイのせん断強さを高める装置および方法を提供することである。
更に本発明の別の目的は、層間剥離の問題を防ぐまたは少なくとも小さくする装置および方法を提供することである。
CuZrのフランジを有するパッケージは他の従来のパッケージより高い費用効果があり、電気的および熱的特性が優れている。
ラフ・エッチには機械的結合機能があり、Siと、Tiなどの接着金属との間の接触面積を大きくする。これにより層間剥離の恐れが更に除かれまたは少なくとも減り、また接着効果が高める。鋭い凹部ピークを除去することによりSi表面の「影」(“shadows”)を除くことができる。かかる「影」があると、蒸着中にSi表面を接着金属で完全に覆うことが一層困難になることがある。
本発明の或る変形では、集積回路ダイの厚さは150μmより薄く、好ましくは約40μmから80μmである。
本発明の或る変形では、フランジはCuとZrとの合金である。
最終Au層を抗酸化層として有し、またこの層を十分厚くすることにより、のこ引きテープをダイから解放することが容易になる。なぜなら、Snの粗い多結晶構造に比べて一層滑らかな表面がAu層により得られるからである。Au表面が滑らかになるほど表面のポリマ残渣がなくなり、これにより空隙の形成を少なくとも減らすことができる。
本発明の或る変形では、第1のAu層は、回路ダイをフランジにはんだ付けするステップの間は拡散隔膜金属層に隣接する第1のAu層の少なくとも一部が固体状態を保持するように形成される。
本発明の或る変形では、フランジは厚さ0.4μmから2.5μmのめっきされたAuの層を含み、はんだ付けのステップの間はこれはダイの上のAuおよびSn層と共に、共晶合成物に比べるとAuリッチの合金を形成する。Auリッチの合金のAuの重量パーセントは86%から89%の間でよい。
本発明の別の特徴および利点は以下の本発明の実施の形態の詳細な説明から明らかになる。
Claims (39)
- それぞれがウェーハからのこ引きされたSi回路ダイをヒートシンクに取り付ける方法であって、
機械的研磨により前記ウェーハを薄くするステップと、
前記ウェーハに等方性湿式化学的エッチを行って結晶欠陥を除くステップと、
前記ウェーハの裏面に接着および拡散隔膜金属を蒸着させるステップと、
前記ウェーハの裏面にAuおよびSnを蒸着させることによりAuおよびSnを追加するステップであって、Auの前記追加したAuおよびSnに対する重量割合は85%以上である追加ステップと、
前記ウェーハをのこ引きして回路ダイを作るステップと、
前記各回路ダイをそれぞれのヒートシンクにはんだ付けするステップであって、前記追加したAuおよびSnがはんだを形成する、はんだ付けステップと、
を含むSi回路ダイを取り付ける方法。 - 前記ヒートシンクは集積回路パッケージのフランジである、請求項1記載のSi回路ダイを取り付ける方法。
- 前記ヒートシンクはRF電力モジュールまたはプリント回路板上のヒートシンクである、請求項1記載のSi回路ダイを取り付ける方法。
- 前記回路ダイは集積回路ダイ、電力トランジスタ、またはコンデンサであり、また前記回路ダイの1つ以上はそれぞれのヒートシンクにはんだ付けされる、請求項1−3の任意の1つの項記載のSi回路ダイを取り付ける方法。
- 前記等方性湿式化学的エッチは等方性スピン・エッチである、請求項1−4の任意の1つの項記載のSi回路ダイを取り付ける方法。
- 前記等方性湿式化学的エッチの後にSi表面にラフ・スピン・エッチを行ってSi表面を粗くするステップを含む、請求項1記載のSi回路ダイを取り付ける方法。
- 前記等方性湿式化学的エッチを行うステップは前記ウェーハ裏面の少なくとも25μmを除去する、請求項1記載のSi回路ダイを取り付ける方法。
- 前記ヒートシンクは純Cu、またはCuとZrまたはCPC材料またはPCM材料との合金である、請求項1記載のSi回路ダイを取り付ける方法。
- 前記ウェーハの裏面にAuおよびSnを追加するステップは、第1のAu層とSn層と第2のAu層とを蒸着させることにより行う、請求項1記載のSi回路ダイを取り付ける方法。
- 前記ウェーハの裏面にAuおよびSnを追加するステップは、第1のAu層とSn層とを蒸着することにより行う、請求項1記載のSi回路ダイを取り付ける方法。
- 前記第1のAu層は、前記回路ダイを前記ヒートシンクにはんだ付けする前記ステップの間は前記拡散隔膜金属層に隣接する前記第1のAu層の少なくとも一部が固体状態を保持するように形成される、請求項10記載のSi回路ダイを取り付ける方法。
- 前記ヒートシンクはめっきされたAuの層を含み、前記はんだ付けのステップの間はウェーハ上のAuおよびSn層と共に、80重量パーセントのAuと20重量パーセントのSnの、AuとSnとの共晶合成物に比べるとAuリッチのはんだを形成する、請求項1記載のSi回路ダイを取り付ける方法。
- 前記Auリッチのはんだは86から89重量パーセントのAuを含む、請求項12記載のSi回路ダイを取り付ける方法。
- 接着および拡散隔膜金属を蒸着させる前記ステップは前記ウェーハの裏面にTi層を蒸着させまたPt層を蒸着させることを含む、請求項1記載のSi回路ダイを取り付ける方法。
- ラフ・エッチの後にラウンドアップ・スピン・エッチを行って鋭い凹部ピークを除去するステップを含む、請求項6記載のSi回路ダイを取り付ける方法。
- ウェーハからのこ引きされてヒートシンクに取り付けられるSi回路ダイを製作する方法であって、
機械的研磨により前記ウェーハを薄くし、
前記ウェーハに等方性湿式化学的エッチを行って結晶欠陥を除き、
前記ウェーハの裏面に接着および拡散隔膜金属を蒸着させ、
前記ウェーハの裏面にAuおよびSnを蒸着させることによりAuおよびSnを追加し、Auの重量割合は前記追加したAuおよびSnの85%以上であり、
前記ウェーハをのこ引きして回路ダイを作る、
ことを含むSi回路ダイを製作する方法。 - 前記ヒートシンクは集積回路パッケージのフランジである、請求項16記載のSi回路ダイを製作する方法。
- 前記ヒートシンクはRF電力モジュールまたはプリント回路板上のヒートシンクである、請求項16記載のSi回路ダイを製作する方法。
- 前記回路ダイは集積回路ダイ、電力トランジスタ、またはコンデンサであり、また前記回路ダイの1つ以上は前記パッケージのそれぞれのフランジにはんだ付けされる、請求項16記載のSi回路ダイを製作する方法。
- 前記等方性湿式化学的エッチは等方性スピン・エッチである、請求項16記載のSi回路ダイを製作する方法。
- 前記等方性湿式化学的エッチの後にSiにラフ・エッチを行ってSi表面を粗くするステップを含む、請求項16記載のSi回路ダイを製作する方法。
- 前記ウェーハの裏面にAuおよびSnを追加するステップは、第1のAu層とSn層と第2のAu層とを蒸着させることにより行う、請求項16記載のSi回路ダイを製作する方法。
- 前記第1のAu層は、前記回路ダイを前記ヒートシンクにはんだ付けする前記ステップの間は前記第1のAu層の少なくとも一部が固体状態を保持するように形成される、請求項22記載のSi回路ダイを製作する方法。
- 前記フランジはめっきされたAuの層を含み、前記はんだ付けのステップの間はダイ上のAuおよびSn層と共にAuリッチのはんだを形成する、請求項16記載のSi回路ダイを製作する方法。
- 前記Auリッチのはんだは86から89重量パーセントのAuを含む、請求項24記載のSi回路ダイを製作する方法。
- 接着および拡散隔膜金属を蒸着させる前記ステップは前記ウェーハの裏面にTi層を蒸着させまたPt層を蒸着させることを含む、請求項16記載のSi回路ダイを製作する方法。
- ラフ・エッチの後にラウンドアップ・エッチを行って鋭い凹部ピークを除去するステップを含む、請求項21記載のSi回路ダイを製作する方法。
- Si回路ダイであって、
ヒートシンクに取り付けられる前記ダイの裏面上の接着および拡散隔膜金属の層と、
AuとSnとの交互の層のスタックであって、前記拡散隔膜金属の層に隣接する前記スタック内の第1の層はAu層であり、前記スタック内の最後の層はAu層であるスタックと、
を含み、
前記スタック内のAuの重量パーセントは85%以上である、
ことを特徴とする回路ダイ。 - 前記回路ダイは集積回路ダイ、電力トランジスタ、コンデンサ、インダクタ、ダイオード、または抵抗器である、請求項28記載の回路ダイ。
- 前記接着および拡散隔膜金属の層はTiの第1の層とPtの第2の層とを含む、請求項28記載の回路ダイ。
- 前記回路ダイの厚さは150μm未満である、請求項28記載の回路ダイ。
- 前記回路ダイの前記裏面は結晶欠陥をほとんどまたは全く含まない、請求項28記載の回路ダイ。
- 前記拡散隔膜金属に隣接する、前記スタック内の前記第1のAu層は、前記ダイをヒートシンクにはんだ付けする間、該第1のAu層の少なくとも一部が固体状態を保持する、請求項28記載の回路ダイ。
- 前記Auの第1の層は、ダイの厚さが60μmを超える場合は3μmから6μmであり、ダイの厚さが60μmに満たない場合は3μmである、請求項33記載の回路ダイ。
- 前記Auの最終の層の厚さは0.5μmから1.0μmである、請求項28記載の回路ダイ。
- 前記AuとSnの交互の層のスタックは3つの層、すなわち、Auの第1の層とSnの層とAuの最終の層とを含む、請求項28記載の回路ダイ。
- 請求項28から36の任意の1つの項記載のフランジおよびSi集積回路を含む回路パッケージであって、前記フランジはCuと、ZrまたはCPC材料またはPCM材料の合金から作られる、回路パッケージ。
- 請求項28から36の任意の1つの項記載のヒートシンクおよびSi集積回路を含む電力モジュールであって、前記ヒートシンクはCuとZrまたはCPC材料またはPCM材料の合金から作られる、電力モジュール。
- 前記AuとSnとのスタック内のAuとSnとの関係は、前記回路ダイを前記集積回路パッケージ上の前記フランジにはんだ付けした後、前記スタック内のAuの重量パーセントが86%から89%でなければならないという要求により決まる、請求項37記載の回路パッケージ。
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EP04445024A EP1575089B1 (en) | 2004-03-09 | 2004-03-09 | Highly reliable, cost effective and thermally enhanced AuSn die-attach technology |
PCT/SE2005/000331 WO2005086220A1 (en) | 2004-03-09 | 2005-03-07 | Highly reliable, cost effective and thermally enhanced ausn die-attach technology |
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Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7327029B2 (en) * | 2005-09-27 | 2008-02-05 | Agere Systems, Inc. | Integrated circuit device incorporating metallurigical bond to enhance thermal conduction to a heat sink |
JP2009054892A (ja) * | 2007-08-28 | 2009-03-12 | Panasonic Electric Works Co Ltd | Ledチップの実装方法 |
US8828804B2 (en) * | 2008-04-30 | 2014-09-09 | Infineon Technologies Ag | Semiconductor device and method |
US7754533B2 (en) * | 2008-08-28 | 2010-07-13 | Infineon Technologies Ag | Method of manufacturing a semiconductor device |
US8637379B2 (en) * | 2009-10-08 | 2014-01-28 | Infineon Technologies Ag | Device including a semiconductor chip and a carrier and fabrication method |
US8994182B2 (en) | 2012-12-21 | 2015-03-31 | Cree, Inc. | Dielectric solder barrier for semiconductor devices |
US8970010B2 (en) | 2013-03-15 | 2015-03-03 | Cree, Inc. | Wafer-level die attach metallization |
JP5877487B1 (ja) * | 2014-12-26 | 2016-03-08 | パナソニックIpマネジメント株式会社 | 発光装置 |
US9893027B2 (en) | 2016-04-07 | 2018-02-13 | Nxp Usa, Inc. | Pre-plated substrate for die attachment |
US10610104B2 (en) | 2016-12-07 | 2020-04-07 | Progenity, Inc. | Gastrointestinal tract detection methods, devices and systems |
CA3045310A1 (en) | 2016-12-14 | 2018-06-21 | Progenity, Inc. | Treatment of a disease of the gastrointestinal tract with a chemokine/chemokine receptor inhibitor |
WO2020106750A1 (en) | 2018-11-19 | 2020-05-28 | Progenity, Inc. | Methods and devices for treating a disease with biotherapeutics |
CN115666704A (zh) | 2019-12-13 | 2023-01-31 | 比奥拉治疗股份有限公司 | 用于将治疗剂递送至胃肠道的可摄取装置 |
CN114171422B (zh) * | 2022-02-11 | 2022-06-03 | 浙江里阳半导体有限公司 | 半导体器件的制造方法及其蒸镀缺陷的检测方法 |
Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS556839A (en) * | 1978-06-28 | 1980-01-18 | Nec Corp | Semiconductor device |
JPS6223118A (ja) * | 1985-07-24 | 1987-01-31 | Hitachi Ltd | 半導体装置 |
JPS63221634A (ja) * | 1987-03-10 | 1988-09-14 | Nippon Mining Co Ltd | 半導体ペレツトの固定方法 |
JPH04156935A (ja) * | 1990-10-19 | 1992-05-29 | Ngk Insulators Ltd | セラミック粒の製造方法 |
JPH04336702A (ja) * | 1991-05-14 | 1992-11-24 | Mitsubishi Electric Corp | パッケージ |
JPH06349866A (ja) * | 1993-06-10 | 1994-12-22 | Sumitomo Electric Ind Ltd | 半導体ウェハ及び半導体素子のダイボンディング方法 |
JPH07130685A (ja) * | 1993-11-05 | 1995-05-19 | Sumitomo Electric Ind Ltd | 半導体ウェーハの製造方法 |
JPH09283909A (ja) * | 1996-04-19 | 1997-10-31 | Hitachi Ltd | 電子回路装置およびその製造方法 |
JPH1070141A (ja) * | 1996-06-28 | 1998-03-10 | Internatl Business Mach Corp <Ibm> | チップ・キャリア・モジュール、情報処理システム及び形成方法 |
JPH1079471A (ja) * | 1996-09-05 | 1998-03-24 | Hitachi Ltd | 半導体装置、その製造方法及びフレキシブルカード |
JPH10326806A (ja) * | 1997-03-28 | 1998-12-08 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
JPH11204884A (ja) * | 1998-01-07 | 1999-07-30 | Mitsubishi Electric Corp | ハンダ形成方法 |
JP2002151541A (ja) * | 2000-11-15 | 2002-05-24 | Hitachi Ltd | 電子部品 |
JP2002270676A (ja) * | 2001-03-12 | 2002-09-20 | Hitachi Ltd | 半導体装置の製造方法 |
JP2003037231A (ja) * | 2001-07-23 | 2003-02-07 | Ibiden Co Ltd | モジュール用基板 |
JP2003200289A (ja) * | 2001-09-27 | 2003-07-15 | Furukawa Electric Co Ltd:The | 部材の接合方法、その方法で得られた接合部材 |
JP2003282751A (ja) * | 2002-03-20 | 2003-10-03 | Sumitomo Metal Electronics Devices Inc | 高周波用パッケージならびに高周波用パワーモジュール基板及びその製造方法 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3648357A (en) * | 1969-07-31 | 1972-03-14 | Gen Dynamics Corp | Method for sealing microelectronic device packages |
JPS5837713B2 (ja) * | 1978-12-01 | 1983-08-18 | 富士通株式会社 | 半導体レ−ザ−装置の製造方法 |
US4518112A (en) * | 1982-12-30 | 1985-05-21 | International Business Machines Corporation | Process for controlled braze joining of electronic packaging elements |
JPS6156422A (ja) * | 1984-08-28 | 1986-03-22 | Nec Corp | 半導体装置 |
US4875617A (en) * | 1987-01-20 | 1989-10-24 | Citowsky Elya L | Gold-tin eutectic lead bonding method and structure |
GB2221570B (en) * | 1988-08-04 | 1992-02-12 | Stc Plc | Bonding a semiconductor to a substrate |
DE4025622A1 (de) * | 1990-08-13 | 1992-02-20 | Siemens Ag | Anschlusskontakthoecker und verfahren zu dessen herstellung |
US5353193A (en) * | 1993-02-26 | 1994-10-04 | Lsi Logic Corporation | High power dissipating packages with matched heatspreader heatsink assemblies |
US5384690A (en) * | 1993-07-27 | 1995-01-24 | International Business Machines Corporation | Flex laminate package for a parallel processor |
GB2300375B (en) * | 1994-08-01 | 1998-02-25 | Nippon Denso Co | Bonding method for electric element |
US6027957A (en) * | 1996-06-27 | 2000-02-22 | University Of Maryland | Controlled solder interdiffusion for high power semiconductor laser diode die bonding |
TW380284B (en) * | 1998-09-09 | 2000-01-21 | Promos Technologies Inc | Method for improving etching uniformity during a wet etching process |
US6180505B1 (en) * | 1999-01-07 | 2001-01-30 | International Business Machines Corporation | Process for forming a copper-containing film |
JP2003068751A (ja) * | 2001-08-27 | 2003-03-07 | Nec Yamagata Ltd | 半導体装置及びその製造方法 |
US6660548B2 (en) * | 2002-03-27 | 2003-12-09 | Intel Corporation | Packaging of multiple active optical devices |
US6833289B2 (en) * | 2003-05-12 | 2004-12-21 | Intel Corporation | Fluxless die-to-heat spreader bonding using thermal interface material |
-
2004
- 2004-03-09 EP EP04445024A patent/EP1575089B1/en not_active Expired - Fee Related
- 2004-03-09 DE DE602004010061T patent/DE602004010061T2/de not_active Expired - Lifetime
-
2005
- 2005-03-07 WO PCT/SE2005/000331 patent/WO2005086220A1/en active Application Filing
- 2005-03-07 JP JP2007502765A patent/JP4700681B2/ja not_active Expired - Fee Related
-
2006
- 2006-09-08 US US11/530,276 patent/US7608485B2/en not_active Expired - Fee Related
Patent Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS556839A (en) * | 1978-06-28 | 1980-01-18 | Nec Corp | Semiconductor device |
JPS6223118A (ja) * | 1985-07-24 | 1987-01-31 | Hitachi Ltd | 半導体装置 |
JPS63221634A (ja) * | 1987-03-10 | 1988-09-14 | Nippon Mining Co Ltd | 半導体ペレツトの固定方法 |
JPH04156935A (ja) * | 1990-10-19 | 1992-05-29 | Ngk Insulators Ltd | セラミック粒の製造方法 |
JPH04336702A (ja) * | 1991-05-14 | 1992-11-24 | Mitsubishi Electric Corp | パッケージ |
JPH06349866A (ja) * | 1993-06-10 | 1994-12-22 | Sumitomo Electric Ind Ltd | 半導体ウェハ及び半導体素子のダイボンディング方法 |
JPH07130685A (ja) * | 1993-11-05 | 1995-05-19 | Sumitomo Electric Ind Ltd | 半導体ウェーハの製造方法 |
JPH09283909A (ja) * | 1996-04-19 | 1997-10-31 | Hitachi Ltd | 電子回路装置およびその製造方法 |
JPH1070141A (ja) * | 1996-06-28 | 1998-03-10 | Internatl Business Mach Corp <Ibm> | チップ・キャリア・モジュール、情報処理システム及び形成方法 |
JPH1079471A (ja) * | 1996-09-05 | 1998-03-24 | Hitachi Ltd | 半導体装置、その製造方法及びフレキシブルカード |
JPH10326806A (ja) * | 1997-03-28 | 1998-12-08 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
JPH11204884A (ja) * | 1998-01-07 | 1999-07-30 | Mitsubishi Electric Corp | ハンダ形成方法 |
JP2002151541A (ja) * | 2000-11-15 | 2002-05-24 | Hitachi Ltd | 電子部品 |
JP2002270676A (ja) * | 2001-03-12 | 2002-09-20 | Hitachi Ltd | 半導体装置の製造方法 |
JP2003037231A (ja) * | 2001-07-23 | 2003-02-07 | Ibiden Co Ltd | モジュール用基板 |
JP2003200289A (ja) * | 2001-09-27 | 2003-07-15 | Furukawa Electric Co Ltd:The | 部材の接合方法、その方法で得られた接合部材 |
JP2003282751A (ja) * | 2002-03-20 | 2003-10-03 | Sumitomo Metal Electronics Devices Inc | 高周波用パッケージならびに高周波用パワーモジュール基板及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
DE602004010061T2 (de) | 2008-09-11 |
DE602004010061D1 (de) | 2007-12-27 |
JP2007528601A (ja) | 2007-10-11 |
WO2005086220A1 (en) | 2005-09-15 |
US7608485B2 (en) | 2009-10-27 |
EP1575089B1 (en) | 2007-11-14 |
EP1575089A1 (en) | 2005-09-14 |
US20070181987A1 (en) | 2007-08-09 |
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