JPS6156422A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS6156422A
JPS6156422A JP59178706A JP17870684A JPS6156422A JP S6156422 A JPS6156422 A JP S6156422A JP 59178706 A JP59178706 A JP 59178706A JP 17870684 A JP17870684 A JP 17870684A JP S6156422 A JPS6156422 A JP S6156422A
Authority
JP
Japan
Prior art keywords
chip
package
adhered
solder
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59178706A
Other languages
English (en)
Inventor
Kimiaki Katsukawa
勝川　公昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP59178706A priority Critical patent/JPS6156422A/ja
Publication of JPS6156422A publication Critical patent/JPS6156422A/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83009—Pre-treatment of the layer connector or the bonding area
    • H01L2224/83048—Thermal treatments, e.g. annealing, controlled pre-heating or pre-cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13063—Metal-Semiconductor Field-Effect Transistor [MESFET]

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は化合物半導体素子、特にＧａＡｓＭＥＳＦＥＴ
及び該Ｍ１８ＰＥＴを基本素子としたモノリシツクＩＣ
チツプの裏面メタル構成に関するものである。
近年、化合物半導体、特にＧａＡｓ、　ＩｎＰ　あるい
はこれらの混晶は高い電子易動度を持ち、高電界におけ
る電子速度の最大飽和値が大きいことから高い遮断周波
数を持つＦＢＴが実現できる材料として注目されておシ
、現在Ｃ帯、Ｘ帯、　Ｋｕ帯、に帯で動作する素子とし
て低雑音化、高出力化、高利得化、高効率化、そしてさ
らなる高周波化、モノリシックＩＯへの展開の為の開発
、製品化が行なわれている。
〔従来の技術〕
従来、この種の素子の裏面メタルの構成は、第３図に示
すように、半導体チップ１の裏面にＴｉ層２．ｐｔ層３
およびＡｕ層４を順次積層する構造を持っていた。
〔発明が解決しようとする問題点」 この構造では、パッケージ６にチップ１をマウントする
際、高温に熱したパッケージ６上にＡｕＳｎソルダー片
５を乗せて溶かし、テップ１を圧着させる工程をとる為
、ソルダー片５０表面酸化膜やスラッジによりチップ１
とソルダー５及びパッケージ６とソルダー５の１ぬれ１
が悪く、又ソルダー５中のボイド発生によシ、熱抵抗の
増大やチップ剥離の不具合が発生するなどの難点があっ
た。
本発明の目的はチップとパッケージの均一な接着性の向
上によシ、熱抵抗増大、チップ剥離の不具合を抑制し、
さらにソルダー片を設置する工数を削減することにある
。
〔問題点を解決するための手段〕
本発明は、化合物半導体材料を用いた半導体チップの裏
面にＡｕとＳｎとを含む金属層を被着したことを特徴と
する０ ？　　　　　　　好ましは、その金属層はｓ　Ａｕ層と
Ｓｎ層とを最後がＡｕ層となるように交互に積層したも
のであり、また、Ａｕ８ｎの合金スパッター膜（Ａｕ：
１８〜２２瓜址パーセント）である。
〔実施例〕
第１図は本発明の一実施例による半導体装置の構造断面
図である。本構造のチップ１は裏面メタルとしてＴｉ−
Ｐを人ｕ２，３．４の上にさらにＡｕＳｎ層７のスパッ
ター膜を持ち、さらに最表面層にＡｕ層８を持つ。
本構造によれば、第１図に示す如く、アらかじめチップ
１の裏面に均一にソルダーが付着していることと等価で
あシ、チップ１とソルダーとの１ぬれ“の問題は解消さ
れる。又チップ裏面の最表面層がＡｕである為、酸化膜
の形成もない。又、チップマウント工程において、ソル
ダー片を設置する工数が削減できるだけでなく、チップ
をパッケージ上に置くだけで熱履歴を通せばチップマウ
ントは完了する為、・自動化が可能となる。
次に本発明の具体的実施例を示す。
ＧａＡｓＭＥＳＦＥＴの表面素子形成の完了したウ　　
　　　　（エバーの裏面を厚さ約１４０μとなるように
ウェハー研磨を行なう。次にＴｉ　−ＰをＡｕを各２０
００Ｘ順次被着し、さらにＡｕＳｎ合金（Ａｕ：２０重
量パーセント）のスパッター膜を被着しさらにＡｕ薄膜
を被着する０このクエ／Ｓ−をダイシングによシ固々の
チップに分割し、ＧａＡｓＭＥＳＦＥＴチップを作製す
る。
該チップを、あらかじめ２９００ｄに予備加熱した゛セ
ラミックパッケージのチップマウント箇所に設置しチッ
プのパッケージへの接着を行なう０その結果、素子の熱
抵抗バラツキは極めて小さく、しかもＸ線によるボイド
観察チェックでもボイドの発生は従来方法に比較し、極
めて少ないことがわかり、当初の目的を果すことができ
る。
以上本発明の一実施例として特定な方法、材料で説明し
たが本技術思想から明らかなように、本実施例に限定さ
れることなく適用されることはいうまでもない。また、
実験の結果、ＡｕＳｎ　ｆａ　７において、Ａｕが５．
８から６．４重量パーセント又は１８から２２ｆｆｉｉ
１パーセントで合一まれだもので、チップマウント性、
熱抵抗、およびボイド発生の抑制に最も効果があること
がわかったＯ第２図に本発明の他の実施例を示す。Ｇａ
ＡｓＭＢＳＦＥＴの表面素子形成の完了したウェハーの
裏面を厚さ約１４０μとなるようにウェハー研磨を行な
う。次にＴｉ　２−Ｐｔ　３−Ａｕ　４ｅ各２０００１
順次被着しさらにＡｕと８ｎを交互に重量％でＡｕが２
０チの比（Ｓｎ　ｒｉｃｈ　）となる膜厚比で２１層被
着、して交互積層膜９を形成する。このウェハーをダイ
シングによシ、ＧａＡｓＭＥＳＦＥＴチップを作製する
。
このチップを、あらかじめ２９０℃に予備加熱したセラ
ミックパッケージのチップマウンド箇所に設置し、チッ
プのパッケージへの接着を行なう。
その結果、第１図で示したように、素子の熱抵抗バラツ
キは極めて小さく、シかも、Ｘ１ｌｉＩＫよるボイド観
察チェックでもボイド発生は従来方法に比較し極めて少
ないことがわがシ当初の目的を果すことができる。
以上本発明の一実施例として特定な方法、材料で説明し
たが本技術思想から明らかなように本実施例に限定され
ることなく適用されることはいうまでもない。
〔発明の効果〕
以上のとおり、本発明によればチップマウント性が改善
されて、熱抵抗低減、剥離防止が可能となった半導体装
置が提供される。
【図面の簡単な説明】
第１図は本発明の一実施例を示す斜視図、第２図は他の
実施例を示す斜視図、第３図は従来例を示す斜視図であ
る。 １・・・・・・半導体チップ、２・・・・・・Ｔ１層、
３・・・・・・ｐｔ層、４・・・・・・Ａｕｊ！、５・
・・・・・λｕｓｎ　ソルダー、６・・・・・・パッケ
ージ、７・・・・・・ＡｕＳｎ合金スパッター膜、８・
・・・・・Ａｕ磨、９・・・・・・Ａｕ、Ｓｎ交互積層
膜第　１　回 稟　２　図 第　３　国

Claims (1)

  1. 【特許請求の範囲】 １、化合物半導体材料を用いた半導体チップの裏面にＡ
    ｕとＳｎとを含む金属層が被着されていることを特徴と
    する半導体装置。 ２、前記金属層は、Ａｕ層とＳｎ層とを最後がＡｕ層と
    なりかつＡｕの重量パーセントが１８から２２となるよ
    うに交互に積層した金属層であることを特徴とする特許
    請求の範囲第１項記載の半導体装置。 ３、前記金属層は、ＡｕＳｎの合金層（Ａｕ：１８−２
    ２重量パーセント）とその表面を覆うＡｕ層とでなるこ
    とを特徴とする特許請求の範囲第１項記載の半導体装置
    。
JP59178706A 1984-08-28 1984-08-28 半導体装置 Pending JPS6156422A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59178706A JPS6156422A (ja) 1984-08-28 1984-08-28 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59178706A JPS6156422A (ja) 1984-08-28 1984-08-28 半導体装置

Publications (1)

Publication Number Publication Date
JPS6156422A true JPS6156422A (ja) 1986-03-22

Family

ID=16053135

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59178706A Pending JPS6156422A (ja) 1984-08-28 1984-08-28 半導体装置

Country Status (1)

Country Link
JP (1) JPS6156422A (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0253691A2 (en) * 1986-06-17 1988-01-20 Fairchild Semiconductor Corporation Silicon die bonding process
JPS63142638A (ja) * 1986-12-05 1988-06-15 Sumitomo Electric Ind Ltd 半導体装置の製造方法
JPH01149428A (ja) * 1987-12-07 1989-06-12 Nec Corp 半導体装置
FR2646018A1 (fr) * 1989-04-12 1990-10-19 Mitsubishi Electric Corp Dispositif semiconducteur et son procede de fabrication
WO2005086220A1 (en) * 2004-03-09 2005-09-15 Infineon Technologies Ag Highly reliable, cost effective and thermally enhanced ausn die-attach technology

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0253691A2 (en) * 1986-06-17 1988-01-20 Fairchild Semiconductor Corporation Silicon die bonding process
JPS63142638A (ja) * 1986-12-05 1988-06-15 Sumitomo Electric Ind Ltd 半導体装置の製造方法
JPH01149428A (ja) * 1987-12-07 1989-06-12 Nec Corp 半導体装置
FR2646018A1 (fr) * 1989-04-12 1990-10-19 Mitsubishi Electric Corp Dispositif semiconducteur et son procede de fabrication
WO2005086220A1 (en) * 2004-03-09 2005-09-15 Infineon Technologies Ag Highly reliable, cost effective and thermally enhanced ausn die-attach technology
US7608485B2 (en) 2004-03-09 2009-10-27 Infineon Technologies Ag Highly reliable, cost effective and thermally enhanced AuSn die-attach technology

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