JP4642094B2 - 発光装置及び電子機器 - Google Patents
発光装置及び電子機器 Download PDFInfo
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- JP4642094B2 JP4642094B2 JP2008122600A JP2008122600A JP4642094B2 JP 4642094 B2 JP4642094 B2 JP 4642094B2 JP 2008122600 A JP2008122600 A JP 2008122600A JP 2008122600 A JP2008122600 A JP 2008122600A JP 4642094 B2 JP4642094 B2 JP 4642094B2
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Description
このように、従来において、電流源回路を内蔵した信号線駆動回路は提案されている。(例えば、非特許文献1、2参照)
服部励治、他3名、「信学技報」、ED2001−8、電流指定型ポリシリコンTFTアクティブマトリクス駆動有機LEDディスプレイの回路シミュレーション、p.7−14 Reiji H et al.、「AM−LCD’01」、OLED−4, p.223−226
本実施の形態では、本発明の信号線駆動回路に具備される図1に示した電流源回路420の回路構成の例とその動作について説明する。
図19(および図6(B)、図33(B)、図35(A)など)に示した電流源回路では、1本の信号線ごと(各列)に2つの電流源回路を設けて、一方の電流源回路で設定動作を行い、他方の電流源回路で入力動作を行うように設定することが好ましいことは上述した。これは、設定動作と入力動作とを同時に行うことが出来ないためである。本実施の形態では、図2に示した第1電流源回路421又は第2電流源回路422の構成とその動作について図8を用いて説明する。
本実施の形態では、本発明の信号線駆動回路が具備される発光装置の構成について図15を用いて説明する。
本実施の形態では、図15(A)に示した信号線駆動回路403の構成とその動作について説明する。本実施の形態では、1ビットのデジタル階調表示を行う場合に用いる信号線駆動回路403について図3を用いて説明する。
本実施の形態では、図15(A)に示した信号線駆動回路403の詳細な構成とその動作について説明するが、本実施の形態では、3ビットのデジタル階調表示を行う場合に用いる信号線駆動回路403について説明する。
なお本発明では、端子aから入力される設定信号とは、第1シフトレジスタ415から供給されるサンプリングパルスに相当する。つまり電流源回路420の設定は、第1シフトレジスタから供給されるサンプリングパルスに合わせて行う。また本実施の形態では、3ビットのデジタル階調表示を行う場合を例に挙げて説明する関係上、1本の信号線ごと(各列)に3つの電流源回路420が設けられている。1本の信号線に接続された3つの電流源回路420から供給される信号電流Idataを1:2:4として設定すると、23=8段階で電流の大きさを制御出来る。
電流源回路に電流を供給するリファレンス用定電流源109は、基板上に信号線駆動回路と一体形成してもよいし、IC等を用いて基板の外部に配置してもよい。基板上に一体形成する場合には、図6〜8、図31〜図35に示した電流源回路のいずれを用いて形成してもよい。或いは、単に1個のトランジスタを配置して、ゲートに加える電圧に応じて、電流値を制御するようにしてもよい。本実施の形態では、リファレンス用定電流源109の一例について説明する。
上記形態では、主に、信号電流制御スイッチが存在する場合について述べてきた。本実施の形態では、信号電流制御スイッチが無い場合、つまり、信号線とは異なる別の配線に、ビデオ信号には比例しない電流(一定の電流)を供給する場合について述べる。この場合にはスイッチ101(信号電流制御スイッチ)を配置する必要はない。
本発明の実施の形態について、図52を用いて説明する。図52(A)において、画素部の上方に信号線駆動回路、下方に定電流回路を配置し、前記信号線駆動回路に電流源A、定電流回路に電流源Bを配置する。電流源A、Bから供給される電流をIA、IBとし、画素に供給される信号電流をIdataとすると、IA=IB+Idataが成立する。そして、画素に信号電流を書き込む際には、電流源A、Bの両者から電流を供給するように設定する。このとき、IA、IBを大きくすると、画素に対する信号電流の書き込み速度を早くすることができる。
図13(B)の画素は、信号線1151、第1及び第2の走査線1142、1143、電流線(電源線)1144、スイッチング用TFT1145、保持用TFT1146、変換駆動用TFT1147、駆動用TFT1148、容量素子1149、発光素子1140とを有する。信号線1151は電流源回路1141に接続されている。
また、異方導電性フィルム4300は導電性フィラー4300aを有している。基板4001とFPC4006とを熱圧着することで、基板4001上の導電性膜4203aとFPC4006上のFPC用配線4301とが、導電性フィラー4300aによって電気的に接続される。
Claims (5)
- 信号線駆動回路と、走査線駆動回路と、走査線及び信号線に対応して複数の画素がマトリクス状に配置された画素部と、を有する発光装置であって、
前記複数の画素は、各々、発光素子を有し、
前記信号線駆動回路は、第1のシフトレジスタ回路と、第2のシフトレジスタ回路と、ラッチ回路と、前記信号線毎に設けられる電流源回路及び第1のスイッチと、を有し、
前記第1のシフトレジスタ回路は、第1のパルスを出力する機能を有し、
前記第2のシフトレジスタ回路は、第2のパルスを出力する機能を有し、
前記ラッチ回路は、前記第1のパルスに応じてビデオ信号を記憶する機能を有し、
前記電流源回路は、第1のトランジスタと、第2のトランジスタと、容量素子と、第2のスイッチと、第3のスイッチと、を有し、
前記第1のトランジスタのソース及びドレインの一方が電源と接続され、
前記容量素子の一方の電極が前記第1のトランジスタのソース及びドレインの一方と接続され、前記容量素子の他方の電極が前記第1のトランジスタのゲートと接続され、
前記第2のトランジスタのソース及びドレインの一方が前記第1のトランジスタのソース及びドレインの他方と接続され、前記第2のトランジスタのソース及びドレインの他方が前記第1のスイッチを介して前記信号線と接続され、前記第2のトランジスタのゲートが前記第1のトランジスタのゲートと接続され、
前記第2のスイッチの一方の端子が前記第1のトランジスタのゲートと接続され、前記第2のスイッチの他方の端子が前記第1のトランジスタのソース及びドレインの他方と接続され、
前記第3のスイッチの一方の端子が第1の電流が供給される配線と接続され、前記第3のスイッチの他方の端子が前記第1のトランジスタのソース及びドレインの他方と接続され、
前記第1のスイッチは、前記ラッチ回路に記憶された前記ビデオ信号によりオン又はオフが制御され、
前記第2のスイッチ及び前記第3のスイッチは、前記第2のパルスに応じた信号によりオン又はオフが制御され、
前記第2のスイッチ及び前記第3のスイッチがオンであることによって、前記第2のトランジスタがオフになり、前記第1のトランジスタに前記第1の電流が供給され、前記第1の電流に応じた電圧が前記容量素子に保持され、
前記第2のスイッチ及び前記第3のスイッチがオフであり、且つ前記第1のスイッチがオンであることによって、前記容量素子に保持された前記電圧に応じた第2の電流が前記第1のトランジスタ、前記第2のトランジスタ及び前記第1のスイッチを介して前記信号線に出力されることを特徴とする発光装置。 - 信号線駆動回路と、走査線駆動回路と、走査線及び信号線に対応して複数の画素がマトリクス状に配置された画素部と、を有する発光装置であって、
前記複数の画素は、各々、発光素子を有し、
前記信号線駆動回路は、第1のシフトレジスタ回路と、デコーダ回路と、ラッチ回路と、前記信号線毎に設けられる電流源回路及び第1のスイッチと、を有し、
前記第1のシフトレジスタ回路は、第1のパルスを出力する機能を有し、
前記デコーダ回路は、第2のパルスを出力する機能を有し、
前記ラッチ回路は、前記第1のパルスに応じてビデオ信号を記憶する機能を有し、
前記電流源回路は、第1のトランジスタと、第2のトランジスタと、容量素子と、第2のスイッチと、第3のスイッチと、を有し、
前記第1のトランジスタのソース及びドレインの一方が電源と接続され、
前記容量素子の一方の電極が前記第1のトランジスタのソース及びドレインの一方と接続され、前記容量素子の他方の電極が前記第1のトランジスタのゲートと接続され、
前記第2のトランジスタのソース及びドレインの一方が前記第1のトランジスタのソース及びドレインの他方と接続され、前記第2のトランジスタのソース及びドレインの他方が前記第1のスイッチを介して前記信号線と接続され、前記第2のトランジスタのゲートが前記第1のトランジスタのゲートと接続され、
前記第2のスイッチの一方の端子が前記第1のトランジスタのゲートと接続され、前記第2のスイッチの他方の端子が前記第1のトランジスタのソース及びドレインの他方と接続され、
前記第3のスイッチの一方の端子が第1の電流が供給される配線と接続され、前記第3のスイッチの他方の端子が前記第1のトランジスタのソース及びドレインの他方と接続され、
前記第1のスイッチは、前記ラッチ回路に記憶された前記ビデオ信号によりオン又はオフが制御され、
前記第2のスイッチ及び前記第3のスイッチは、前記第2のパルスに応じた信号によりオン又はオフが制御され、
前記第2のスイッチ及び前記第3のスイッチがオンであることによって、前記第2のトランジスタがオフになり、前記第1のトランジスタに前記第1の電流が供給され、前記第1の電流に応じた電圧が前記容量素子に保持され、
前記第2のスイッチ及び前記第3のスイッチがオフであり、且つ前記第1のスイッチがオンであることによって、前記容量素子に保持された前記電圧に応じた第2の電流が前記第1のトランジスタ、前記第2のトランジスタ及び前記第1のスイッチを介して前記信号線に出力されることを特徴とする発光装置。 - 信号線駆動回路と、走査線駆動回路と、走査線及び信号線に対応して複数の画素がマトリクス状に配置された画素部と、を有する発光装置であって、
前記複数の画素は、各々、発光素子を有し、
前記信号線駆動回路は、第1のシフトレジスタ回路と、第2のシフトレジスタ回路と、ラッチ回路と、前記信号線毎に設けられる第1の電流源回路、第2の電流源回路及び第1のスイッチと、を有し、
前記第1のシフトレジスタ回路は、第1のパルスを出力する機能を有し、
前記第2のシフトレジスタ回路は、第2のパルスを出力する機能を有し、
前記ラッチ回路は、前記第1のパルスに応じてビデオ信号を記憶する機能を有し、
前記第1の電流源回路及び前記第2の電流源回路は、各々、第1のトランジスタと、第2のトランジスタと、容量素子と、第2のスイッチと、第3のスイッチと、第4のスイッチと、第5のスイッチと、を有し、
前記第1のトランジスタのソース及びドレインの一方が電源と接続され、
前記容量素子の一方の電極が前記第1のトランジスタのソース及びドレインの一方と接続され、前記容量素子の他方の電極が前記第1のトランジスタのゲートと接続され、
前記第2のトランジスタのソース及びドレインの一方が前記第1のトランジスタのソース及びドレインの他方と接続され、前記第2のトランジスタのソース及びドレインの他方が前記第1のスイッチを介して前記信号線と接続され、前記第2のトランジスタのゲートが前記第1のトランジスタのゲートと接続され、
前記第2のスイッチ及び前記第4のスイッチが前記第1のトランジスタのゲートと前記第1のトランジスタのソース及びドレインの他方との間に直列に接続され、
前記第3のスイッチ及び前記第5のスイッチが第1の電流が供給される配線と前記第1のトランジスタのソース及びドレインの他方との間に直列に接続され、
前記第1のスイッチは、前記ラッチ回路に記憶された前記ビデオ信号によりオン又はオフが制御され、
前記第2のスイッチ前記第3のスイッチは、前記第2のパルスに応じた信号によりオン又はオフが制御され、
前記第4のスイッチ及び前記第5のスイッチは、制御信号によりオン又はオフが制御され、
前記第2のスイッチ、前記第3のスイッチ、前記第4のスイッチ及び前記第5のスイッチがオンであることによって、前記第2のトランジスタがオフになり、前記第1のトランジスタに前記第1の電流が供給され、前記第1の電流に応じた電圧が前記容量素子に保持され、
前記第2のスイッチ、前記第3のスイッチ、前記第4のスイッチ及び前記第5のスイッチがオフであり、且つ前記第1のスイッチがオンであることによって、前記容量素子に保持された前記電圧に応じた第2の電流が前記第1のトランジスタ、前記第2のトランジスタ及び前記第1のスイッチを介して前記信号線に出力されることを特徴とする発光装置。 - 請求項3において、
前記第1の電流源回路及び前記第2の電流源回路の一方において、前記第2のスイッチ、前記第3のスイッチ、前記第4のスイッチ及び前記第5のスイッチがオンであるとき、前記第1の電流源回路及び前記第2の電流源回路の他方において、前記第2のスイッチ、前記第3のスイッチ、前記第4のスイッチ及び前記第5のスイッチがオフであることを特徴とする発光装置。 - 請求項1乃至請求項4のいずれか一項に記載の発光装置を具備する電子機器。
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US20030128199A1 (en) | 2003-07-10 |
US8624802B2 (en) | 2014-01-07 |
US20120235974A1 (en) | 2012-09-20 |
SG152054A1 (en) | 2009-05-29 |
KR20050042006A (ko) | 2005-05-04 |
TW200300544A (en) | 2003-06-01 |
WO2003038795A1 (fr) | 2003-05-08 |
KR100939734B1 (ko) | 2010-02-01 |
CN100476927C (zh) | 2009-04-08 |
US20070146249A1 (en) | 2007-06-28 |
EP1447787A1 (en) | 2004-08-18 |
JP2008203884A (ja) | 2008-09-04 |
TWI252454B (en) | 2006-04-01 |
US8164548B2 (en) | 2012-04-24 |
EP1447787A4 (en) | 2009-07-01 |
CN1610932A (zh) | 2005-04-27 |
US7180479B2 (en) | 2007-02-20 |
JPWO2003038795A1 (ja) | 2005-02-24 |
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