JP4638456B2 - ラッチアップ防止を有する調整可能なボディバイアス生成回路網 - Google Patents

ラッチアップ防止を有する調整可能なボディバイアス生成回路網 Download PDF

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Publication number
JP4638456B2
JP4638456B2 JP2007044383A JP2007044383A JP4638456B2 JP 4638456 B2 JP4638456 B2 JP 4638456B2 JP 2007044383 A JP2007044383 A JP 2007044383A JP 2007044383 A JP2007044383 A JP 2007044383A JP 4638456 B2 JP4638456 B2 JP 4638456B2
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Japan
Prior art keywords
body bias
power supply
transistor
signal
latch
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Expired - Fee Related
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JP2007044383A
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Japanese (ja)
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JP2007243179A (ja
JP2007243179A5 (enExample
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ペリセティ スリニバス
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Altera Corp
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Altera Corp
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Publication of JP2007243179A5 publication Critical patent/JP2007243179A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/854—Complementary IGFETs, e.g. CMOS comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0018—Special modifications or use of the back gate voltage of a FET

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
JP2007044383A 2006-03-06 2007-02-23 ラッチアップ防止を有する調整可能なボディバイアス生成回路網 Expired - Fee Related JP4638456B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/369,548 US7330049B2 (en) 2006-03-06 2006-03-06 Adjustable transistor body bias generation circuitry with latch-up prevention

Publications (3)

Publication Number Publication Date
JP2007243179A JP2007243179A (ja) 2007-09-20
JP2007243179A5 JP2007243179A5 (enExample) 2010-03-11
JP4638456B2 true JP4638456B2 (ja) 2011-02-23

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JP2007044383A Expired - Fee Related JP4638456B2 (ja) 2006-03-06 2007-02-23 ラッチアップ防止を有する調整可能なボディバイアス生成回路網

Country Status (4)

Country Link
US (2) US7330049B2 (enExample)
EP (1) EP1840965B1 (enExample)
JP (1) JP4638456B2 (enExample)
CN (1) CN101034882B (enExample)

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100605591B1 (ko) * 2005-01-31 2006-07-31 주식회사 하이닉스반도체 반도체 소자의 승압전압 발생기
CN101238641B (zh) * 2005-08-02 2010-09-08 松下电器产业株式会社 半导体集成电路
US7495471B2 (en) * 2006-03-06 2009-02-24 Altera Corporation Adjustable transistor body bias circuitry
US7355437B2 (en) 2006-03-06 2008-04-08 Altera Corporation Latch-up prevention circuitry for integrated circuits with transistor body biasing
US7696811B2 (en) * 2006-06-19 2010-04-13 International Business Machines Corporation Methods and circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications
US7459958B2 (en) * 2006-06-19 2008-12-02 International Business Machines Corporation Circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications
JP2008004741A (ja) * 2006-06-22 2008-01-10 Matsushita Electric Ind Co Ltd 半導体集積回路及びそれを備えた情報機器、通信機器、ａｖ機器及び移動体
US20080180129A1 (en) * 2006-08-31 2008-07-31 Actel Corporation Fpga architecture with threshold voltage compensation and reduced leakage
US8242742B2 (en) * 2007-06-06 2012-08-14 O2Micro, Inc Chargers, systems and methods for detecting a power source
FR2921756B1 (fr) 2007-09-27 2009-12-25 Commissariat Energie Atomique Matrice de pixels dotes de regulateurs de tension.
FR2921788B1 (fr) * 2007-10-01 2015-01-02 Commissariat Energie Atomique Dispositif microelectronique a matrice de pixels dote de moyens generateurs de compensation de chute ohmique sur des almentations
US7639041B1 (en) 2008-07-28 2009-12-29 Altera Corporation Hotsocket-compatible body bias circuitry with power-up current reduction capabilities
CN103109525B (zh) * 2008-10-08 2016-04-06 法国原子能委员会 一种矩阵微电子装置
US8742831B2 (en) * 2009-02-23 2014-06-03 Honeywell International Inc. Method for digital programmable optimization of mixed-signal circuits
US7911261B1 (en) 2009-04-13 2011-03-22 Netlogic Microsystems, Inc. Substrate bias circuit and method for integrated circuit device
US9142951B2 (en) 2009-07-28 2015-09-22 Stmicroelectronics (Rousset) Sas Electronic device for protecting against a polarity reversal of a DC power supply voltage, and its application to motor vehicles
FR2948828B1 (fr) * 2009-07-28 2011-09-30 St Microelectronics Rousset Dispositif electronique de protection contre une inversion de polarite d'une tension d'alimentation continue, et application au domaine de l'automobile
US8618786B1 (en) 2009-08-31 2013-12-31 Altera Corporation Self-biased voltage regulation circuitry for memory
JP2011060358A (ja) * 2009-09-08 2011-03-24 Elpida Memory Inc 半導体装置及びその制御方法
KR101699033B1 (ko) * 2009-11-30 2017-01-24 에스케이하이닉스 주식회사 출력 드라이버
US9208109B2 (en) * 2011-06-01 2015-12-08 Altera Corporation Memory controllers with dynamic port priority assignment capabilities
US9350321B2 (en) * 2011-08-18 2016-05-24 Analog Devices, Inc. Low distortion impedance selection and tunable impedance circuits
US8698516B2 (en) * 2011-08-19 2014-04-15 Altera Corporation Apparatus for improving performance of field programmable gate arrays and associated methods
US8970289B1 (en) 2012-01-23 2015-03-03 Suvolta, Inc. Circuits and devices for generating bi-directional body bias voltages, and methods therefor
FR2988239A1 (fr) * 2012-03-16 2013-09-20 Converteam Technology Ltd Procede de compensation des tolerances de fabrication d'au moins un parametre electrique d'un transistor de puissance et systeme associe
KR102038041B1 (ko) * 2012-08-31 2019-11-26 에스케이하이닉스 주식회사 전원 선택 회로
US8787096B1 (en) * 2013-01-16 2014-07-22 Qualcomm Incorporated N-well switching circuit
US9112495B1 (en) * 2013-03-15 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit device body bias circuits and methods
CN104464788B (zh) * 2014-12-30 2017-06-06 上海华虹宏力半导体制造有限公司 分压电路、操作电压的控制电路及存储器
US9591245B2 (en) 2015-04-14 2017-03-07 Semiconductor Components Industries, Llc Image sensor pixels with adjustable body bias
US9584118B1 (en) * 2015-08-26 2017-02-28 Nxp Usa, Inc. Substrate bias circuit and method for biasing a substrate
US9762833B1 (en) * 2016-05-24 2017-09-12 Omnivision Technologies, Inc. Adaptive body biasing circuit for latch-up prevention
DK3343769T3 (da) * 2016-12-27 2019-05-06 Gn Hearing As Integreret kredsløb, der omfatter justerbar spærreforspænding af én eller flere logiske kredsløbsregioner
CN107659303A (zh) * 2017-08-31 2018-02-02 晨星半导体股份有限公司 输入输出电路
US10552563B2 (en) * 2018-01-10 2020-02-04 Qualcomm Incorporated Digital design with bundled data asynchronous logic and body-biasing tuning
TWI642274B (zh) * 2018-03-20 2018-11-21 大陸商北京集創北方科技股份有限公司 栓鎖偵測電路
CN108270422B (zh) * 2018-03-20 2024-07-12 北京集创北方科技股份有限公司 防闩锁电路及集成电路
US10469097B1 (en) 2018-12-06 2019-11-05 Nxp Usa, Inc. Body bias circuit for current steering DAC switches
CN109814650B (zh) * 2019-01-23 2020-05-22 西安交通大学 一种低压差线性稳压器用箝位晶体管结构
US11099224B2 (en) * 2019-05-24 2021-08-24 Marvell Israel (M.I.S.L) Ltd. Method and circuitry for semiconductor device performance characterization
KR102696754B1 (ko) * 2019-12-30 2024-08-21 에스케이하이닉스 주식회사 데이터 입출력 회로를 포함하는 메모리 장치
US11688739B2 (en) * 2021-03-19 2023-06-27 Pixart Imaging Inc. Logic circuit capable of preventing latch-up
CN113849438B (zh) * 2021-09-27 2024-03-08 浙江华创视讯科技有限公司 保护电路、保护电路的方法、存储介质及电子装置

Family Cites Families (85)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62209846A (ja) * 1986-03-10 1987-09-16 Fujitsu Ltd 半導体集積回路
JPH0783254B2 (ja) * 1989-03-22 1995-09-06 株式会社東芝 半導体集積回路
DE4221575C2 (de) * 1992-07-01 1995-02-09 Ibm Integrierter CMOS-Halbleiterschaltkreis und Datenverarbeitungssystem mit integriertem CMOS-Halbleiterschaltkreis
US5341034A (en) * 1993-02-11 1994-08-23 Benchmarq Microelectronics, Inc. Backup battery power controller having channel regions of transistors being biased by power supply or battery
KR0169157B1 (ko) * 1993-11-29 1999-02-01 기다오까 다까시 반도체 회로 및 mos-dram
US5422591A (en) * 1994-01-03 1995-06-06 Sgs-Thomson Microelectronics, Inc. Output driver circuit with body bias control for multiple power supply operation
JPH08181598A (ja) * 1994-12-27 1996-07-12 Oki Electric Ind Co Ltd 半導体装置
US5689209A (en) * 1994-12-30 1997-11-18 Siliconix Incorporated Low-side bidirectional battery disconnect switch
JP3444687B2 (ja) * 1995-03-13 2003-09-08 三菱電機株式会社 不揮発性半導体記憶装置
US5670907A (en) 1995-03-14 1997-09-23 Lattice Semiconductor Corporation VBB reference for pumped substrates
US5674090A (en) 1995-03-15 1997-10-07 Sumitomo Wiring Systems, Ltd. Casing for receiving electrical connection box
US5631606A (en) * 1995-08-01 1997-05-20 Information Storage Devices, Inc. Fully differential output CMOS power amplifier
JP2931776B2 (ja) * 1995-08-21 1999-08-09 三菱電機株式会社 半導体集積回路
US5600264A (en) 1995-10-16 1997-02-04 Xilinx, Inc. Programmable single buffered six pass transistor configuration
US5689144A (en) * 1996-05-15 1997-11-18 Siliconix Incorporated Four-terminal power MOSFET switch having reduced threshold voltage and on-resistance
KR100189752B1 (ko) * 1996-06-01 1999-06-01 구본준 독립적인 웰 바이어스 전압을 가진 전압 펌프회로
KR100203136B1 (ko) * 1996-06-27 1999-06-15 김영환 래치-업을 방지하는 상승전압발생기
JP3264622B2 (ja) * 1996-07-16 2002-03-11 株式会社東芝 半導体装置
US6411156B1 (en) * 1997-06-20 2002-06-25 Intel Corporation Employing transistor body bias in controlling chip parameters
US6593799B2 (en) * 1997-06-20 2003-07-15 Intel Corporation Circuit including forward body bias from supply voltage and ground nodes
US5841694A (en) * 1997-07-30 1998-11-24 Programmable Silicon Solutions High performance programmable interconnect
US6535034B1 (en) * 1997-07-30 2003-03-18 Programmable Silicon Solutions High performance integrated circuit devices adaptable to use lower supply voltages with smaller device geometries
US6346415B1 (en) * 1997-10-21 2002-02-12 Targeted Genetics Corporation Transcriptionally-activated AAV inverted terminal repeats (ITRS) for use with recombinant AAV vectors
US6097242A (en) * 1998-02-26 2000-08-01 Micron Technology, Inc. Threshold voltage compensation circuits for low voltage and low power CMOS integrated circuits
US6157691A (en) * 1998-04-14 2000-12-05 Lsi Logic Corporation Fully integrated phase-locked loop with resistor-less loop filer
JP3136593B2 (ja) * 1998-08-17 2001-02-19 日本電気株式会社 レギュレータ内蔵半導体装置
US6242728B1 (en) * 1998-08-20 2001-06-05 Foveon, Inc. CMOS active pixel sensor using native transistors
JP3549186B2 (ja) * 1998-08-25 2004-08-04 株式会社東芝 半導体装置
TW453032B (en) * 1998-09-09 2001-09-01 Hitachi Ltd Semiconductor integrated circuit apparatus
JP4384759B2 (ja) * 1998-09-14 2009-12-16 テキサス インスツルメンツ インコーポレイテツド Ｍｏｓ集積回路の特性を改良するためのボディ電圧のパルス動作
US6484265B2 (en) * 1998-12-30 2002-11-19 Intel Corporation Software control of transistor body bias in controlling chip parameters
JP2000269356A (ja) * 1999-03-15 2000-09-29 Hitachi Ltd 半導体装置
US6271713B1 (en) * 1999-05-14 2001-08-07 Intel Corporation Dynamic threshold source follower voltage driver circuit
JP2001034040A (ja) * 1999-07-21 2001-02-09 Sharp Corp 接触帯電装置ならびにそれを備えたプロセスカートリッジおよび画像形成装置
US6448840B2 (en) * 1999-11-30 2002-09-10 Intel Corporation Adaptive body biasing circuit and method
KR100347140B1 (ko) * 1999-12-31 2002-08-03 주식회사 하이닉스반도체 전압 변환 회로
KR20010077099A (ko) * 2000-01-31 2001-08-17 윤종용 자기 정렬된 웰 바이어스 영역을 갖는 모스 트랜지스터 및그 제조방법
JP2001230664A (ja) * 2000-02-15 2001-08-24 Mitsubishi Electric Corp 半導体集積回路
US20020140496A1 (en) * 2000-02-16 2002-10-03 Ali Keshavarzi Forward body biased transistors with reduced temperature
JP2001339045A (ja) * 2000-05-25 2001-12-07 Hitachi Ltd 半導体集積回路装置
US6549032B1 (en) * 2000-08-22 2003-04-15 Altera Corporation Integrated circuit devices with power supply detection circuitry
TW463466B (en) * 2000-08-30 2001-11-11 Silicon Integrated Sys Corp Current A/D converter and the unit cell thereof
TW448617B (en) * 2000-09-15 2001-08-01 Silicon Integrated Sys Corp N-well bias preset circuit for CMOS and the method thereof
US6343044B1 (en) * 2000-10-04 2002-01-29 International Business Machines Corporation Super low-power generator system for embedded applications
US6744301B1 (en) * 2000-11-07 2004-06-01 Intel Corporation System using body-biased sleep transistors to reduce leakage power while minimizing performance penalties and noise
KR100385230B1 (ko) * 2000-12-28 2003-05-27 삼성전자주식회사 불휘발성 반도체 메모리 장치의 프로그램 방법
US6373281B1 (en) * 2001-01-22 2002-04-16 International Business Machines Corporation Tri-state dynamic body charge modulation for sensing devices in SOI RAM applications
US6597203B2 (en) * 2001-03-14 2003-07-22 Micron Technology, Inc. CMOS gate array with vertical transistors
US6429726B1 (en) * 2001-03-27 2002-08-06 Intel Corporation Robust forward body bias generation circuit with digital trimming for DC power supply variation
US6469572B1 (en) * 2001-03-28 2002-10-22 Intel Corporation Forward body bias generation circuits based on diode clamps
US6670655B2 (en) * 2001-04-18 2003-12-30 International Business Machines Corporation SOI CMOS device with body to gate connection
US6605981B2 (en) * 2001-04-26 2003-08-12 International Business Machines Corporation Apparatus for biasing ultra-low voltage logic circuits
GB0111300D0 (en) * 2001-05-09 2001-06-27 Mitel Knowledge Corp Method and apparatus for synchronizing slave network node to master network node
JP2002343083A (ja) * 2001-05-18 2002-11-29 Mitsubishi Electric Corp 半導体装置
US6554249B2 (en) * 2001-05-30 2003-04-29 Fmc Technologies, Inc. Plug valve having seal segments with booster springs
US6518826B2 (en) * 2001-06-28 2003-02-11 Intel Corporation Method and apparatus for dynamic leakage control
US6763484B2 (en) * 2001-06-28 2004-07-13 Intel Corporation Body bias using scan chains
US6483375B1 (en) * 2001-06-28 2002-11-19 Intel Corporation Low power operation mechanism and method
US6559702B2 (en) * 2001-07-19 2003-05-06 Texas Instruments Incorporated Bias generator and method for improving output skew voltage
US6621325B2 (en) * 2001-09-18 2003-09-16 Xilinx, Inc. Structures and methods for selectively applying a well bias to portions of a programmable device
US6630700B2 (en) * 2001-10-05 2003-10-07 Motorola, Inc. NMOS circuit in isolated wells that are connected by a bias stack having pluralirty of diode elements
JP4090231B2 (ja) * 2001-11-01 2008-05-28 株式会社ルネサステクノロジ 半導体集積回路装置
US6650141B2 (en) * 2001-12-14 2003-11-18 Lattice Semiconductor Corporation High speed interface for a programmable interconnect circuit
US6614301B2 (en) * 2002-01-31 2003-09-02 Intel Corporation Differential amplifier offset adjustment
US20030151428A1 (en) * 2002-02-12 2003-08-14 Ouyang Paul H. 5 Volt tolerant input/output buffer
US6525559B1 (en) * 2002-04-22 2003-02-25 Pericom Semiconductor Corp. Fail-safe circuit with low input impedance using active-transistor differential-line terminators
US7254603B2 (en) * 2002-05-03 2007-08-07 Sonics, Inc. On-chip inter-network performance optimization using configurable performance parameters
JP4401621B2 (ja) * 2002-05-07 2010-01-20 株式会社日立製作所 半導体集積回路装置
JP3821047B2 (ja) * 2002-05-09 2006-09-13 富士電機デバイステクノロジー株式会社 電圧可変レギュレータ
US6870213B2 (en) * 2002-05-10 2005-03-22 International Business Machines Corporation EEPROM device with substrate hot-electron injector for low-power
US20030218478A1 (en) * 2002-05-24 2003-11-27 Sani Mehdi Hamidi Regulation of crowbar current in circuits employing footswitches/headswitches
US6731158B1 (en) * 2002-06-13 2004-05-04 University Of New Mexico Self regulating body bias generator
WO2004015867A1 (en) * 2002-08-08 2004-02-19 Koninklijke Philips Electronics N.V. Circuit and method for controlling the threshold voltage of transistors
US6972599B2 (en) * 2002-08-27 2005-12-06 Micron Technology Inc. Pseudo CMOS dynamic logic with delayed clocks
US7120804B2 (en) * 2002-12-23 2006-10-10 Intel Corporation Method and apparatus for reducing power consumption through dynamic control of supply voltage and body bias including maintaining a substantially constant operating frequency
US6972593B1 (en) * 2003-08-05 2005-12-06 Altera Corp. Method and apparatus for protecting a circuit during a hot socket condition
US6975535B2 (en) * 2003-08-14 2005-12-13 Mosel Vitelic, Inc. Electronic memory, such as flash EPROM, with bitwise-adjusted writing current or/and voltage
US7098689B1 (en) * 2003-09-19 2006-08-29 Xilinx, Inc. Disabling unused/inactive resources in programmable logic devices for static power reduction
US6972616B2 (en) * 2004-04-14 2005-12-06 Broadcom Corporation Low-noise, fast-settling bias circuit and method
US7112997B1 (en) * 2004-05-19 2006-09-26 Altera Corporation Apparatus and methods for multi-gate silicon-on-insulator transistors
US7348827B2 (en) * 2004-05-19 2008-03-25 Altera Corporation Apparatus and methods for adjusting performance of programmable logic devices
US7129745B2 (en) * 2004-05-19 2006-10-31 Altera Corporation Apparatus and methods for adjusting performance of integrated circuits
US7119604B2 (en) * 2004-06-17 2006-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Back-bias voltage regulator having temperature and process variation compensation and related method of regulating a back-bias voltage
US20060119382A1 (en) * 2004-12-07 2006-06-08 Shumarayev Sergey Y Apparatus and methods for adjusting performance characteristics of programmable logic devices
JP3905909B2 (ja) * 2005-09-05 2007-04-18 株式会社ルネサステクノロジ 半導体装置

Also Published As

Publication number Publication date
JP2007243179A (ja) 2007-09-20
US20070205802A1 (en) 2007-09-06
US7514953B2 (en) 2009-04-07
CN101034882B (zh) 2012-07-18
EP1840965A3 (en) 2009-11-11
CN101034882A (zh) 2007-09-12
US20080094100A1 (en) 2008-04-24
US7330049B2 (en) 2008-02-12
EP1840965B1 (en) 2013-09-18
EP1840965A2 (en) 2007-10-03

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