JP4566325B2 - 半導体装置を製造する方法 - Google Patents

半導体装置を製造する方法 Download PDF

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Publication number
JP4566325B2
JP4566325B2 JP2000086214A JP2000086214A JP4566325B2 JP 4566325 B2 JP4566325 B2 JP 4566325B2 JP 2000086214 A JP2000086214 A JP 2000086214A JP 2000086214 A JP2000086214 A JP 2000086214A JP 4566325 B2 JP4566325 B2 JP 4566325B2
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Japan
Prior art keywords
layer
forming
barrier layer
conductive barrier
opening
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Expired - Fee Related
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JP2000306914A (ja
JP2000306914A5 (ja
Inventor
アレクサンダー・エル・バール
シュレシュ・ベンカテサン
デイビッド・ビー・クレッグ
レベッカ・ジー・コール
オルブンミ・アデツーツ
ステュアート・イー・グリーア
ブライアン・ジー・アンソニー
ラムナッシュ・ベンカトラマン
グレゴール・ブラエックルマン
ダグラス・エム・レーバー
ステファン・アール・クラウン
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NXP USA Inc
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NXP USA Inc
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Description

【0001】
【発明の属する技術分野】
本発明は一般に半導体装置の製造方法に関し、特に相互接続障壁層を有する半導体装置を製造する方法に関する。
【0002】
【従来の技術および発明が解決しようとする課題】
半導体装置のサイズおよびパッケージが縮少し続けるにつれて、半導体装置の結合パッド上にバンプを形成することが益々一般的になってきている。このバンプは、ワイヤの代わりに、各結合パッドをそれらの対応するパッケージ・リードに電気的に接続するために使用される。この種のバンプには、制御コラプス・チップ接続(C4)バンプ(controlled-collapse chip-connection bump)が含まれる。バンプは一般に、パッド限定金属層(pad limiting metal layer)が結合パッドとバンプとの間に形成されることを要する。パッド限定金属層は一般にクロム(Cr)およびクロム合金を含む。しかしながら、これらクロム含有層は、クラックおよび不規則な粒子境界のような欠陥を有する場合があり、この欠陥はクロム層が結合パッドとバンプ材料を適切に分離する能力を制限してしまう。
【0003】
バンプは一般に、スズ(Sn)および鉛(Pb)のような元素を含む。障壁が結合パッドとバンプとの分離を維持できなくなると、結合パッド内の材料がバンプ内の鉛またはスズと反応し、これら材料の合金が形成される。結合パッドが銅を含む材料である場合、堅くもろい(brittle)合金が形成される。この堅くもろい合金により、クラックひいてはバンプの不良を招いてしまう。さらに、合金化の過程に起因してボイドが形成され、結合パッドおよびバンプ間の接着強度を劣化させることも懸念される。これらの不具合は抵抗を高くし、半導体装置の動作特性に悪影響を与え、半導体装置の動作不良を引き起こしてしまうことが懸念される。
【0004】
【課題を解決するための手段】
上述した課題は、各請求項に記載された半導体装置および方法を利用することにより解決される。
【0005】
【発明の実施の形態】
以下、本発明に関連する実施例を説明するが、本発明はそのような実施例に限定されない。各図において、同様の参照番号は同様の要素を示す。また、図中の各要素は説明の便宜上簡略化されて描かれており、厳密な寸法を表現するものではないことは、当業者にとって明らかであろう。例えば、図中のいくつかの要素は他の要素に比較して強調されて描かれているが、これは本発明の実施例を理解しやすくするためのものである。
【0006】
本発明の各実施例によれば、半導体装置およびその製造方法が提供される。一実施例にあっては、導電性障壁層が相互接続部上を被覆し、その導電性障壁層上を保護層が被覆し、保護層は導電性障壁層の一部に至る開口を有する。他の実施例にあっては、保護層が相互接続部上を被覆し、保護層は相互接続部に至る開口を有し、この開口内において導電性障壁層が相互接続部上を被覆する。
【0007】
図1は、半導体装置の部分断面図を示す。半導体装置は、半導体装置基板100、フィールド絶縁領域102、および半導体装置基板100内に形成されたドープ領域104を有する。ゲート誘電体層106は半導体装置基板100の一部を被覆し、ゲート電極108はゲート誘電体層106を被覆する。
【0008】
第1合金誘電体層(ILD: interlevel dielectric layer)110は、ゲート電極108および半導体装置基板100上に形成される。第1合金誘電体層110はパターニングされ、接着/障壁層112および銅充填材料114で満たされる貫通孔(dual inlaid opening)が形成される。接着/障壁層112は一般に、耐熱金属(refractory metal)、耐熱金属窒化物、または耐熱金属若しくはそれらの窒化物の組み合わせである。銅充填材料114は一般に銅や銅合金であり、同含有率が少なくとも90原子パーセントである。銅は、マグネシウム、硫黄、炭素等とともに合金化され、接着性、エレクトロマイグレーションその他の特性を改善する。接着/障壁層112および銅充填材料114を堆積した後、基板は研磨され、接着/障壁層112および銅充填材料114の開口外側の部分が除去される。
【0009】
第1相互接続レベル(階層)が形成された後、絶縁障壁層122が銅充填接続部および第1ILD層110上に形成される。この絶縁障壁層122としては、シリコン窒化物、シリコン・オキシナイトライド(oxynitride)等を利用することが可能である。絶縁障壁層122を形成するために絶縁材料を利用すると、付加的なパターニングおよびエッチングの工程を省略することが可能になる。導電性の障壁が使用されるならば、互いに絶縁させるためにそのような付加的な工程が必要となるであろう。第2ILD層124は絶縁障壁層122上に形成される。導電性の接着/障壁層126および銅充填材料128より成る両面相互接続部(dual inlaid interconnect)が、第2ILD124内に形成される。両面相互接続部は、第1ILD層110の両面相互接続部を形成するために使用したものと同様のプロセスおよび材料を利用して形成される。
【0010】
図2に示されるように、その後保護層22が第2ILD層124および両面相互接続部上に形成される。保護層は、シリコン窒化物、シリコン・オキシナイトライド、二酸化シリコン等の1以上の膜で形成することも可能である。一般に、銅充填材料128に最も近い保護層22の部分は、酸素原子よりも濃度の高い窒素原子を有するシリコン窒化物またはシリコン・オキシナイトライドとすることが可能である。保護層22はパターニングされ、その保護層を貫通して銅充填材料128に至る結合パッド開口24が形成される。
【0011】
図3に示すように、保護層22および銅充填材料128上に導電性障壁層32が堆積される。導電性障壁層32は様々なプロセスを利用して堆積させることが可能であり、そのプロセスには、化学蒸着堆積(CVD)、物理蒸着堆積(PVD)、エバポレーション堆積、電気めっき、非電気めっき(electroless plating)等が含まれる。この層の厚さは一般に50ないし300ナノメートル(nm)の範囲内にある。一般に、導電性障壁層32は耐熱金属、耐熱金属窒化物またはこれらの組み合わせを利用することが可能である。一実施例にあっては、導電性障壁層32は、チタニウム(Ti)およびチタニウム窒化物(TiN)の組み合わせより成る。チタニウム/チタニウム窒化物のスタック(積層)を利用すると、下側の銅充填材料128および保護層22との接着性を向上させることが可能である。さらに、チタニウム窒化物は、銅充填材料が以後堆積される導電性バンプと反応することを抑制する障壁層を形成する。また、導電性障壁層32としては、タンタル(Ta)、タンタル窒化物(TaN)、タングステン(W)、チタニウム・タングステン窒化物(TiWN)、チタニウム・タングステン(TiW)、タングステン窒化物(WN)、モリブデン窒化物(MoN)、コバルト窒化物(CoN)またはこれらの組み合わせを利用することが可能である。他の実施例にあっては、酸素耐性材料(oxygen tolerant material)を利用することも可能である。これらの材料には、プラチナ(Pt)、パラジウム(Pd)、ニッケル(Ni)、導電性金属酸化物またはこれらの金属に相当するものが含まれる。導電性金属酸化物およびこれらに相当する金属としては更に、イリジウム(Ir)およびイリジウム酸化物(IrO2)、ルテニウム(Ru)およびルテニウム酸化物(RuO2)、レニウム(Re)およびレニウム酸化物(ReO2およびReO3)、ならびにオスミウム(Os)およびオスミウム酸化物(OsO2)が含まれる。
【0012】
その後レジスト層34が導電性障壁層32上に形成される。レジスト層34は、保護層22を被覆する導電性障壁層32の一部を露出させている。このレジストは、結合パッド開口34を被覆するように形成される。さらに、図3に示すように、保護層22上に位置する導電性障壁層32の一部の表面上にわずかに延在するように、レジストがパターニングされる。
【0013】
その後既存のエッチング工程を利用して、導電性障壁層32はエッチングされ、保護層22上の導電性障壁層32の露出した部分が除去される。エッチング工程の後、パターニングされたレジスト層34は、プラズマ・アッシング工程またはウエット・ケミカル・エッチング工程を利用して除去され、このウエット・ケミカル・エッチング工程は、N-メチル-2-ピロリジン(N-methyl-2-pyrrolidine)、アセトン、メチル・イソブチル・ケトン(MIBK: methyl isobutyl ketone)のような有機化合物を利用するものである。
【0014】
また、電気めっきまたは非電気めっきのようなめっき工程を利用して導電性障壁層を形成する場合、上述したパターニング工程は必ずしも必要とされない。その代わりに、開口24を形成した後、導電性障壁層を銅充填材料128の露出部分上に直接めっきすることが可能である。もし必要であれば、めっきされた材料が保護層の一部分上を被覆するようにめっき処理工程を拡張し、図4に示すような導電性障壁層32を形成することも可能である。
【0015】
図5に示されるように、その後ダイ被覆層52が半導体装置上に形成されパターニングされ、結合パッド開口24上にダイ被覆開口(die coat opening)54が形成される。この実施例にあっては、導電性障壁層32の周辺部分はダイ被覆開口54内で露出した端部領域を有する。ダイ被覆層52は、感光性ポリイミド膜、または既存のレジストおよびエッチング工程を利用してパターニングされるポリイミド膜と同様にして形成することが可能である。
【0016】
図6に示されるようなパッド限定金属層62を形成するのに先立って、導電性障壁層32の露出した部分は、無線周波数(RF)スパッタ洗浄工程による処理が施される。このRFスパッタ洗浄は、導電性障壁層32の最も上側の部分を除去することにより、障壁層とパッド限定金属層との間の接触抵抗を改善するものである。除去される部分には、酸素、フッ素および塩素のような不純物が含まれている可能性がある。一実施例にあっては、RFスパッタ洗浄工程は、パッド限定金属層(バンプ下側)を堆積する前のその場所における(in situ)プロセスの一部として実行される。一実施例にあっては、RFスパッタ洗浄を行うための処理パラメータは、次のようなものである。RF電力が約1200ないし1500ワット(W)の範囲内にあり、直流(DC)バイアス電圧が約(−300)ないし(−600)ボルト(V)であり、圧力が約0.1ないし0.5パスカルの範囲内にあり、時間は約150ないし250秒の範囲内にある。RFスパッタ洗浄工程は、障壁層32の表面から約20−40nmの障壁材料を除去する。
【0017】
図6に示されるように、その後パッド限定金属層62がダイ被覆開口54内に形成される。パッド限定金属層は一般に、薄膜の機能的な組み合わせとすることが可能であり、その薄膜には、接着層、中間結合/半田層および非酸化障壁層等がある。一実施例にあっては、パッド限定金属層62は4つの個別薄膜より成る。すなわち、クロム層622、クロム−銅合金層624、銅層626および金層628である。クロム層622およびクロム−銅合金層624は夫々50ないし500nmの範囲内の厚さを有し、銅層626は約700ないし1300nmの範囲内の厚さを有し、金層628は80ないし140nmの範囲内の厚さを有する。また、パッド限定金属層は、チタニウム、銅および金の複合物またはチタニウム、ニッケル、銅および金の複合物のような他の薄膜の組み合わせとすることも可能である。パッド限定金属層62は一般に、浅いマスクを利用してエバポレーションにより形成される。しかしながら、スパッタリングのような他の手法を利用してパッド限定金属層を形成することも可能である。
【0018】
図7に示されるように一実施例によれば、パッド限定金属層を形成した後に、鉛スズ半田材料72のようなバンプ材料がパッド限定金属層62上に堆積される。鉛スズ半田材料72は浅いマスクを利用してエバポレーションにより形成することが可能であり、また、めっき又は半田ジェット(solderjetting)のような既存の他の手法を利用して形成することも可能である。その後リフロー工程が行われ、鉛スズ半田材料72の角を丸め、図7に示されるようなバンプが形成される。
【0019】
この時点において、実質的には半導体装置は完成している。その後この装置は、フリップ・チップまたはボール・グリッド・アレイ・パッケージのようなパッケージ基板に接着される。図示されてはいないが、必要に応じて相互接続部の他のレベル(階層)を形成することも可能である。他の相互接続部も同様に、ゲート電極108およびドープ領域104に対して形成することが可能である。このような付加的な相互接続部を形成するには、絶縁層122、第2ILD層124、接着/障壁層126および銅充填材料128を形成および堆積するのに使用したものと同様のプロセスを利用することが可能であろう。
【0020】
図8ないし12は、本発明の他の実施例に関するものである。図8では、導電性障壁層82が第2ILD層124および銅充填材料128上に形成されている。導電性障壁層82は、図3の第1実施例の導電性障壁層32を形成する際に説明した方法および材料を利用して形成される。導電性障壁層82の厚さは一般に50ないし300nmの範囲内にある。この実施例にあっては、選択的な耐酸化層(oxidation-resistant)84が導電性障壁層82上に形成されている。耐酸化層としては、下側の層の酸化を防止する又は下側の層に優先して容易に酸化されやすい任意の材料を利用することが可能である。使用可能な材料としては、シリコン窒化物、ポリシリコン、アモルファス・シリコンまたは導電性金属酸化物若しくはその金属等がある。耐酸化層84は約10−50nmの範囲内の厚さを有する。その後、この導電性障壁層82および耐酸化層84上にレジスト層86が形成される。レジスト層86はパターニングされ、導電性障壁層82の一部と、銅充填材料128および接着/障壁層126上の耐酸化層84とが被覆される。
【0021】
導電性障壁層82および耐酸化層84のパターニングされていない部分は、既存のエッチング工程を利用して除去される。その後レジストは除去され、図9に示されるように、導電性障壁層82、耐酸化層84および誘電体層124の一部より成る積層(スタック)上に保護層92形成される。保護層92は、図2の第1実施例の保護層22と同様のものである。この実施例にあっては、保護層92はパターニングされ、結合パッド開口94が形成される。図9に図示されているように、結合パッド開口94内の保護層の総てが除去されるわけではない。したがって、結合パッド開口は、パターニング工程において部分的に形成されるに過ぎない。残余の部分96は、パターニングが完了した後も耐酸化層84上にとり残される。
【0022】
図10に示されるように、ダイ被覆開口1003を形成およびパターニングするためにダイ被覆層1001が形成される。このダイ被覆層1001は図5の第1実施例のダイ被覆層52と同様のものである。ダイ被覆開口1003は、残余部分96を含む保護層92の一部を露出させる。ダイ被覆開口1003を形成した後、エッチングが行われ、残余部分96および下側の耐酸化層84が除去される。このようにして、図11に示されるようなダイ被覆開口1003が形成される。このエッチングにおいて、ダイ被覆層1001により露出させられた保護層92の部分もエッチングされ、これは除去された保護層部分1102として図示されている。一実施例にあっては、保護層92はシリコン窒化物またはシリコン・オキシナイトライドのようなシリコンおよび窒素を含み、耐酸化層84はシリコン窒化物を含む。このため、同一のまたは同様のエッチング環境を利用して、保護層92の残余部分96および耐酸化層84を除去することが可能である。
【0023】
その後プロセスが進行すると、図12に示されるように装置が実質的に完成する。パッド限定金属層1220が、先に説明したものと同様に形成され、この層は、クロム層1222、クロム−銅層1224、銅層1226、金層1228および鉛スズ半田1230を含む。上述したものと同様に、必要に応じてRFスパッタ洗浄工程を利用して、パッド限定金属層1220を形成するのに先立って障壁層の表面に処理を施すことも可能である。この実施例にあっては、リフロー工程を実行し、鉛スズ半田の形状を丸くし、図12に示されるようなドーム状の形を形成する。
【0024】
図9ないし12に関連する実施例にあっては、最上部の相互接続レベルを除く総ての相互接続レベルに対して、絶縁障壁層122が使用される。最上部の相互接続レベルは、結合パッドが形成される部分上の相互接続レベルである。したがって、最上部の相互接続レベルは、導電性障壁層82を利用する唯一の相互接続レベルである。
【0025】
本発明に関連して多数の実施例が存在し得る。図3に戻って、導電性障壁層32は、図8−12の第2実施例の耐酸化層84と同様な耐酸化被覆層を利用することも可能である。同様に、第2実施例は耐酸化層84を必ずしも必要としない。なぜなら、保護層92の残余部分96は、導電性障壁層82に損傷を与えることなく酸素含有プラズマを利用することを許容するからである。このことは次のような場合に特に重要である。すなわち導電性障壁層82または32が、酸素含有プラズマまたはレジストやポリイミドを除去・現像するための他の化学物質に対して適切に反応することが可能なタンタル窒化物、チタニウム窒化物等を含む場合である。このような化学物質の例としては、テトラメチル・アンモニウム水酸化物(tetramethyl ammonium hydroxide)、N-メトキシ-2-ピロリジン、アセトンMIBK等がある。
【0026】
図9−12で説明したような結合パッド上に導電性障壁層を形成することに加えて、導電性障壁材料を利用して、半導体装置の導電性領域間にレーザ可変接続部または集束エネルギ可変(focused energy-alterable)接続部を形成することも可能である。プログラム又は装置の回路に適合させるために、その接続部の導電率はレーザを利用して修正されることが可能である。
【0027】
導電性障壁層を利用するレーザ可変接続部を形成すると、既存の技術に比較して有利な点がある。レーザ可変接続部を形成するために通常使用される導電性障壁層は一般に、相互接続層よりも、非常に薄く、熱伝導性が低く、耐熱性が低い。導電性障壁層は、相互接続層に比較して自ら保護するもの(self-passivating)もある。したがって、レーザ可変が実行された後の短絡に対する電位は減少させられるので、レーザ可変の信頼性は大幅に向上する。さらに、レーザ可変接続部は、半導体装置の最上部表面に近接して形成される。このため、レーザ可変接続部を修正するために使用するレーザの電力は少なくてすみ、それに応じて短絡、接続部近傍への損傷および包囲する保護層の損傷も少なくなる。さらに、導電性障壁層およびレーザ可変接続部は、同一の層を利用して同時に形成されることも可能である。従ってこの場合は、製造工程数を増加させる必要はなくなる。
【0028】
パッド限定金属層62に対していくつかの材料が列挙されたが、必要に応じてたの材料を利用することも可能であろう。例えば、導電性障壁層は、パッド限定金属層の一部として組み込むことも可能である。この場合は、他のパッド限定金属層が形成される前に、ウエファ上にそれをエバポレーション又はスパッタリングにより形成することも可能である。更なる実施例にあっては、パッド限定金属層およびはんだ材料は、物理的蒸着堆積(PVD)により又は噴霧塗布(jet printing)により集約的に形成され、溶融した半田のしたたりが、オリフィス近辺の場所に堆積される。
【0029】
以上説明した実施例は、新種の材料、新プロセスの開発または新装置の購入を必要とすることなく、既存の処理工程に組み込まれることが可能である。導電性障壁層32および82は、相互接続部からの銅およびバンプからの鉛スズ半田が、互いに反応してしまうことを充分に防止する。このため、バンプおよび相互接続部間のインターフェースにおける完全性ないし信頼性が向上する。このことは、バンプの機械的信頼性だけでなく、バンプおよび相互接続部間の電気抵抗を減少させることにも寄与する。
【0030】
以上本発明をいくつかの実施例とともに説明してきた。しかしながら、実施例および図面は、本発明を限定的に解釈させようとするものではない。当業者であれば、本発明の精神から逸脱することなく、様々な修正や改良等をすることが可能であろう。
【図面の簡単な説明】
【図1】本発明の第1実施例による銅の接続部およびバンプを有する半導体装置を形成する工程における部分断面図を示す。
【図2】本発明の第1実施例による銅の接続部およびバンプを有する半導体装置を形成する工程における部分断面図を示す。
【図3】本発明の第1実施例による銅の接続部およびバンプを有する半導体装置を形成する工程における部分断面図を示す。
【図4】本発明の第1実施例による銅の接続部およびバンプを有する半導体装置を形成する工程における部分断面図を示す。
【図5】本発明の第1実施例による銅の接続部およびバンプを有する半導体装置を形成する工程における部分断面図を示す。
【図6】本発明の第1実施例による銅の接続部およびバンプを有する半導体装置を形成する工程における部分断面図を示す。
【図7】本発明の第1実施例による銅の接続部およびバンプを有する半導体装置を形成する工程における部分断面図を示す。
【図8】本発明の第2実施例による銅の接続部およびバンプを有する半導体装置を形成する工程における部分断面図を示す。
【図9】本発明の第2実施例による銅の接続部およびバンプを有する半導体装置を形成する工程における部分断面図を示す。
【図10】本発明の第2実施例による銅の接続部およびバンプを有する半導体装置を形成する工程における部分断面図を示す。
【図11】本発明の第2実施例による銅の接続部およびバンプを有する半導体装置を形成する工程における部分断面図を示す。
【図12】本発明の第2実施例による銅の接続部およびバンプを有する半導体装置を形成する工程における部分断面図を示す。
【符号の説明】
22 保護層
24 開口
32 導電性障壁層
34 レジスト
52 ダイ・コート層
54 開口
62 パッド限定金属層
72 鉛スズ半田材料
82 導電性障壁層
84 耐酸化層
86 レジスト
92 保護層
94 開口
96 保護層の残余部分
100 半導体装置基板
102 フィールド絶縁層
104 ドープ領域
106 ゲート誘電体
108 ゲート電極
110 第1合金誘電体(ILD)層
112 接着/障壁層
114 相互接続部
122 絶縁障壁層
124 第2合金誘電体(ILD)層
126 接着/障壁層
128 銅含有相互接続部
1001 ダイ被覆層
1003 開口
1220 パッド限定金属層
1230 導電性バンプ

Claims (5)

  1. 半導体装置を製造する方法であって、
    半導体装置基板(100)上に第1相互接続部(114)を形成する段階と、
    前記第1相互接続部(114)の一部を覆うように第2相互接続部(128)を形成する段階であって、第2相互接続部(128)は、結合パッド部を含む銅相互接続部としての特徴を有している段階と、
    前記結合パッド部上に導電性障壁層(82)を形成する段階と、
    前記導電性障壁層上に耐酸化層(84)を形成する段階と、
    前記耐酸化層上に保護層(92)を形成する段階と、
    前記保護層(92)に開口(94)の一部を形成する段階であって、前記開口の一部の深さは、同開口の一部が形成される保護層の領域において同保護層の厚さより小さい段階と、
    前記保護層(92)上にダイ被覆層(1001)を形成する段階と、
    前記ダイ被覆層(1001)に開口(1003)を形成する段階であって、前記ダイ被覆層に開口(1003)を形成する段階は、前記保護層(92)の開口(94)の一部を露出させ、かつ前記保護層において前記保護層(92)の開口(94)の一部のエッジ領域周辺の保護層を除去する段階を含む段階と、
    前記ダイ被覆層(1001)に開口(1003)を形成した後、前記導電性障壁層(82)を露出させるため、前記保護層(92)の開口(94)を介してエッチングを行う段階と、
    前記導電性障壁層(82)上にパッド限定金属層(1220)を形成する段階であって、前記パッド限定金属層(1220)はクロム層を含み、前記クロム層は前記導電性障壁層(82)と接触する段階と、
    前記パッド限定金属層(1220)上に導電性バンプ(1230)を形成する段階と
    を備える方法。
  2. 前記導電性障壁層(82)の一部は、少なくとも2つの導電性領域の間に位置するレーザ可変接続部である請求項1記載の方法。
  3. 前記耐酸化層(84)は、シリコン窒化物を含むか、或いは、前記耐酸化層は、シリコン層である請求項1記載の方法。
  4. 前記導電性障壁層(82)は、チタニウム、タンタル、及びタングステンからなる群より選ばれた材料を含むか、或いは、タンタル窒化物、チタニウムタングステン窒化物、チタニウムタングステン、タングステン窒化物、モリブデン窒化物及びコバルト窒化物のうち少なくとも一つを含むか、或いは、プラチナ、パラジウム及びニッケルのうち少なくとも一つを含むか、或いは、イリジウム、イリジウム酸化物、ルテニウム、ルテニウム酸化物、レニウム、レニウム酸化物、オスミウム及びオスミウム酸化物のうち少なくとも一つを含む請求項1記載の方法。
  5. 前記導電性障壁層(82)は、耐熱金属及び耐熱金属窒化物の組合せを含むか、或いは、チタニウム及びチタニウム窒化物を含む請求項1記載の方法。
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JP2000306914A (ja) 2000-11-02
US20020093098A1 (en) 2002-07-18

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