JP4564272B2 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
JP4564272B2
JP4564272B2 JP2004085051A JP2004085051A JP4564272B2 JP 4564272 B2 JP4564272 B2 JP 4564272B2 JP 2004085051 A JP2004085051 A JP 2004085051A JP 2004085051 A JP2004085051 A JP 2004085051A JP 4564272 B2 JP4564272 B2 JP 4564272B2
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Japan
Prior art keywords
trench
inclination angle
semiconductor device
aspect ratio
silicon substrate
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Expired - Lifetime
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JP2004085051A
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English (en)
Japanese (ja)
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JP2005276930A5 (enExample
JP2005276930A (ja
Inventor
孝典 松本
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Toshiba Corp
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Toshiba Corp
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Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2004085051A priority Critical patent/JP4564272B2/ja
Priority to US11/085,112 priority patent/US20050221579A1/en
Priority to KR1020050023520A priority patent/KR100707899B1/ko
Priority to CNB2005100560678A priority patent/CN100377332C/zh
Publication of JP2005276930A publication Critical patent/JP2005276930A/ja
Publication of JP2005276930A5 publication Critical patent/JP2005276930A5/ja
Priority to US11/611,030 priority patent/US7781293B2/en
Application granted granted Critical
Publication of JP4564272B2 publication Critical patent/JP4564272B2/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Drying Of Semiconductors (AREA)
JP2004085051A 2004-03-23 2004-03-23 半導体装置およびその製造方法 Expired - Lifetime JP4564272B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2004085051A JP4564272B2 (ja) 2004-03-23 2004-03-23 半導体装置およびその製造方法
US11/085,112 US20050221579A1 (en) 2004-03-23 2005-03-22 Semiconductor device and method of fabricating the same
KR1020050023520A KR100707899B1 (ko) 2004-03-23 2005-03-22 반도체 장치 및 그 제조 방법
CNB2005100560678A CN100377332C (zh) 2004-03-23 2005-03-23 半导体器件及其制造方法
US11/611,030 US7781293B2 (en) 2004-03-23 2006-12-14 Semiconductor device and method of fabricating the same including trenches of different aspect ratios

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004085051A JP4564272B2 (ja) 2004-03-23 2004-03-23 半導体装置およびその製造方法

Publications (3)

Publication Number Publication Date
JP2005276930A JP2005276930A (ja) 2005-10-06
JP2005276930A5 JP2005276930A5 (enExample) 2006-03-16
JP4564272B2 true JP4564272B2 (ja) 2010-10-20

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JP2004085051A Expired - Lifetime JP4564272B2 (ja) 2004-03-23 2004-03-23 半導体装置およびその製造方法

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US (2) US20050221579A1 (enExample)
JP (1) JP4564272B2 (enExample)
KR (1) KR100707899B1 (enExample)
CN (1) CN100377332C (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013177576A1 (en) * 2012-05-25 2013-11-28 The Regents Of The University Of California Method for fabrication of high aspect ratio trenches and formation of nanoscale features therefrom
US10896803B2 (en) 2016-08-19 2021-01-19 The Regents Of The University Of California Ion beam mill etch depth monitoring with nanometer-scale resolution

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JP4564272B2 (ja) 2004-03-23 2010-10-20 株式会社東芝 半導体装置およびその製造方法
JP4533358B2 (ja) 2005-10-18 2010-09-01 キヤノン株式会社 インプリント方法、インプリント装置およびチップの製造方法
US8936995B2 (en) * 2006-03-01 2015-01-20 Infineon Technologies Ag Methods of fabricating isolation regions of semiconductor devices and structures thereof
KR100801062B1 (ko) * 2006-07-07 2008-02-04 삼성전자주식회사 트렌치 소자 분리 방법, 이를 이용한 게이트 구조물 형성방법 및 불 휘발성 메모리 소자 형성 방법
KR100800379B1 (ko) * 2006-08-29 2008-02-01 삼성전자주식회사 비휘발성 메모리 소자의 게이트 제조방법
KR100913004B1 (ko) * 2006-09-06 2009-08-20 주식회사 하이닉스반도체 반도체 소자의 트랜치 형성 방법
JP4389229B2 (ja) * 2006-12-20 2009-12-24 エルピーダメモリ株式会社 半導体装置の製造方法
US20080197378A1 (en) * 2007-02-20 2008-08-21 Hua-Shuang Kong Group III Nitride Diodes on Low Index Carrier Substrates
JP2009049230A (ja) * 2007-08-21 2009-03-05 Panasonic Corp 半導体記憶装置及びその製造方法
JP2010272758A (ja) * 2009-05-22 2010-12-02 Hitachi High-Technologies Corp 被エッチング材のプラズマエッチング方法
US8138093B2 (en) * 2009-08-12 2012-03-20 International Business Machines Corporation Method for forming trenches having different widths and the same depth
KR101666645B1 (ko) * 2010-08-05 2016-10-17 삼성전자주식회사 다양한 소자 분리 영역들을 갖는 반도체 소자의 제조 방법
FR2999335B1 (fr) * 2012-12-06 2016-03-11 Commissariat Energie Atomique Procede ameliore de realisation d'un composant a structure suspendue et d'un transistor co-integres sur un meme substrat.
CN104217985A (zh) * 2013-05-31 2014-12-17 中芯国际集成电路制造(上海)有限公司 半导体器件和浅沟槽的制作方法
CN105336696A (zh) * 2014-06-18 2016-02-17 上海华力微电子有限公司 一种同时改善STI和FG Poly填充孔洞工艺窗口的方法
CN105470201A (zh) * 2014-06-18 2016-04-06 上海华力微电子有限公司 一种同时改善STI和FG Poly填充空洞的闪存器件工艺方法
MX2018002975A (es) * 2015-10-16 2018-06-11 Ford Global Tech Llc Sistema y metodo para asistencia de seudonavegacion en un vehículo.
JP6591291B2 (ja) 2016-01-07 2019-10-16 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US10593678B1 (en) * 2018-08-24 2020-03-17 Micron Technology, Inc. Methods of forming semiconductor devices using aspect ratio dependent etching effects, and related semiconductor devices
CN114242726A (zh) * 2021-12-16 2022-03-25 上海华虹宏力半导体制造有限公司 闪存存储器及其制造方法

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JP3309620B2 (ja) * 1995-01-27 2002-07-29 富士電機株式会社 ドライエッチングによる部品の製造方法
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013177576A1 (en) * 2012-05-25 2013-11-28 The Regents Of The University Of California Method for fabrication of high aspect ratio trenches and formation of nanoscale features therefrom
US9653309B2 (en) 2012-05-25 2017-05-16 The Regents Of The University Of California Method for fabrication of high aspect ratio trenches and formation of nanoscale features therefrom
US10896803B2 (en) 2016-08-19 2021-01-19 The Regents Of The University Of California Ion beam mill etch depth monitoring with nanometer-scale resolution

Also Published As

Publication number Publication date
CN1674248A (zh) 2005-09-28
US20070082458A1 (en) 2007-04-12
US7781293B2 (en) 2010-08-24
KR100707899B1 (ko) 2007-04-16
KR20060044527A (ko) 2006-05-16
US20050221579A1 (en) 2005-10-06
JP2005276930A (ja) 2005-10-06
CN100377332C (zh) 2008-03-26

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