CN100377332C - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN100377332C
CN100377332C CNB2005100560678A CN200510056067A CN100377332C CN 100377332 C CN100377332 C CN 100377332C CN B2005100560678 A CNB2005100560678 A CN B2005100560678A CN 200510056067 A CN200510056067 A CN 200510056067A CN 100377332 C CN100377332 C CN 100377332C
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China
Prior art keywords
groove
mentioned
semiconductor substrate
angle
ratio
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Expired - Lifetime
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CNB2005100560678A
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English (en)
Chinese (zh)
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CN1674248A (zh
Inventor
松本孝典
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japanese Businessman Panjaya Co ltd
Kioxia Corp
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Toshiba Corp
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Publication of CN1674248A publication Critical patent/CN1674248A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Drying Of Semiconductors (AREA)
CNB2005100560678A 2004-03-23 2005-03-23 半导体器件及其制造方法 Expired - Lifetime CN100377332C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2004085051 2004-03-23
JP2004085051A JP4564272B2 (ja) 2004-03-23 2004-03-23 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
CN1674248A CN1674248A (zh) 2005-09-28
CN100377332C true CN100377332C (zh) 2008-03-26

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Family Applications (1)

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CNB2005100560678A Expired - Lifetime CN100377332C (zh) 2004-03-23 2005-03-23 半导体器件及其制造方法

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US (2) US20050221579A1 (enExample)
JP (1) JP4564272B2 (enExample)
KR (1) KR100707899B1 (enExample)
CN (1) CN100377332C (enExample)

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JP4564272B2 (ja) 2004-03-23 2010-10-20 株式会社東芝 半導体装置およびその製造方法
JP4533358B2 (ja) 2005-10-18 2010-09-01 キヤノン株式会社 インプリント方法、インプリント装置およびチップの製造方法
US8936995B2 (en) * 2006-03-01 2015-01-20 Infineon Technologies Ag Methods of fabricating isolation regions of semiconductor devices and structures thereof
KR100801062B1 (ko) * 2006-07-07 2008-02-04 삼성전자주식회사 트렌치 소자 분리 방법, 이를 이용한 게이트 구조물 형성방법 및 불 휘발성 메모리 소자 형성 방법
KR100800379B1 (ko) * 2006-08-29 2008-02-01 삼성전자주식회사 비휘발성 메모리 소자의 게이트 제조방법
KR100913004B1 (ko) * 2006-09-06 2009-08-20 주식회사 하이닉스반도체 반도체 소자의 트랜치 형성 방법
JP4389229B2 (ja) * 2006-12-20 2009-12-24 エルピーダメモリ株式会社 半導体装置の製造方法
US20080197378A1 (en) * 2007-02-20 2008-08-21 Hua-Shuang Kong Group III Nitride Diodes on Low Index Carrier Substrates
JP2009049230A (ja) * 2007-08-21 2009-03-05 Panasonic Corp 半導体記憶装置及びその製造方法
JP2010272758A (ja) * 2009-05-22 2010-12-02 Hitachi High-Technologies Corp 被エッチング材のプラズマエッチング方法
US8138093B2 (en) * 2009-08-12 2012-03-20 International Business Machines Corporation Method for forming trenches having different widths and the same depth
KR101666645B1 (ko) * 2010-08-05 2016-10-17 삼성전자주식회사 다양한 소자 분리 영역들을 갖는 반도체 소자의 제조 방법
US9653309B2 (en) 2012-05-25 2017-05-16 The Regents Of The University Of California Method for fabrication of high aspect ratio trenches and formation of nanoscale features therefrom
FR2999335B1 (fr) * 2012-12-06 2016-03-11 Commissariat Energie Atomique Procede ameliore de realisation d'un composant a structure suspendue et d'un transistor co-integres sur un meme substrat.
CN104217985A (zh) * 2013-05-31 2014-12-17 中芯国际集成电路制造(上海)有限公司 半导体器件和浅沟槽的制作方法
CN105336696A (zh) * 2014-06-18 2016-02-17 上海华力微电子有限公司 一种同时改善STI和FG Poly填充孔洞工艺窗口的方法
CN105470201A (zh) * 2014-06-18 2016-04-06 上海华力微电子有限公司 一种同时改善STI和FG Poly填充空洞的闪存器件工艺方法
MX2018002975A (es) * 2015-10-16 2018-06-11 Ford Global Tech Llc Sistema y metodo para asistencia de seudonavegacion en un vehículo.
JP6591291B2 (ja) 2016-01-07 2019-10-16 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US10896803B2 (en) 2016-08-19 2021-01-19 The Regents Of The University Of California Ion beam mill etch depth monitoring with nanometer-scale resolution
US10593678B1 (en) * 2018-08-24 2020-03-17 Micron Technology, Inc. Methods of forming semiconductor devices using aspect ratio dependent etching effects, and related semiconductor devices
CN114242726A (zh) * 2021-12-16 2022-03-25 上海华虹宏力半导体制造有限公司 闪存存储器及其制造方法

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US5807784A (en) * 1995-05-30 1998-09-15 Samsung Electronics Co., Ltd. Device isolation methods for a semiconductor device
CN1064779C (zh) * 1996-01-11 2001-04-18 现代电子产业株式会社 半导体器件中的隔离方法
US6495294B1 (en) * 1999-10-28 2002-12-17 Denso Corporation Method for manufacturing semiconductor substrate having an epitaxial film in the trench
US6576558B1 (en) * 2002-10-02 2003-06-10 Taiwan Semiconductor Manufacturing Company High aspect ratio shallow trench using silicon implanted oxide
JP2003303817A (ja) * 2002-02-07 2003-10-24 Tokyo Electron Ltd エッチング方法
US20040014281A1 (en) * 2002-07-18 2004-01-22 Hynix Semiconductor Inc. Method of manufacturing flash memory device using trench device isolation process

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JPH03196624A (ja) * 1989-12-26 1991-08-28 Sony Corp ドライエッチング方法
JP3229058B2 (ja) 1993-02-05 2001-11-12 株式会社リコー 充填溝分離領域を有する半導体装置の製造方法
KR100192178B1 (ko) * 1996-01-11 1999-06-15 김영환 반도체 소자의 아이솔레이션 방법
JPH09289313A (ja) * 1996-04-19 1997-11-04 Sony Corp 半導体装置におけるしきい値電圧の設定方法
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US6303460B1 (en) * 2000-02-07 2001-10-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method for manufacturing the same
KR19990055775A (ko) * 1997-12-27 1999-07-15 김영환 트랜치를 이용한 반도체 소자의 소자분리 방법
US6060370A (en) * 1998-06-16 2000-05-09 Lsi Logic Corporation Method for shallow trench isolations with chemical-mechanical polishing
US6159801A (en) * 1999-04-26 2000-12-12 Taiwan Semiconductor Manufacturing Company Method to increase coupling ratio of source to floating gate in split-gate flash
JP4666700B2 (ja) * 1999-08-30 2011-04-06 富士通セミコンダクター株式会社 半導体装置の製造方法
KR100555490B1 (ko) * 1999-10-15 2006-03-03 삼성전자주식회사 반도체소자의 트렌치 아이솔레이션 형성 방법
US6303447B1 (en) * 2000-02-11 2001-10-16 Chartered Semiconductor Manufacturing Ltd. Method for forming an extended metal gate using a damascene process
JP4200626B2 (ja) * 2000-02-28 2008-12-24 株式会社デンソー 絶縁ゲート型パワー素子の製造方法
JP2002043413A (ja) 2000-07-25 2002-02-08 Toshiba Corp 半導体装置及び半導体装置の製造方法
JP3601439B2 (ja) * 2000-10-31 2004-12-15 セイコーエプソン株式会社 画像表示装置
US6667223B2 (en) * 2001-07-13 2003-12-23 Infineon Technologies Ag High aspect ratio high density plasma (HDP) oxide gapfill method in a lines and space pattern
JP2003060024A (ja) * 2001-08-13 2003-02-28 Mitsubishi Electric Corp 半導体装置の製造方法および半導体装置
US7018929B2 (en) * 2002-07-02 2006-03-28 Taiwan Semiconductor Manufacturing Co., Ltd Method for reducing a low volatility byproduct from a wafer surface following an etching process
KR100443126B1 (ko) 2002-08-19 2004-08-04 삼성전자주식회사 트렌치 구조물 및 이의 형성 방법
JP2004087843A (ja) * 2002-08-27 2004-03-18 Toshiba Corp 半導体装置
JP2004095886A (ja) * 2002-08-30 2004-03-25 Fujitsu Ltd 半導体装置及びその製造方法
KR100481558B1 (ko) * 2002-09-09 2005-04-08 동부아남반도체 주식회사 에어 갭 특성을 이용한 반도체 ｓｔｉ 형성 방법
US7482178B2 (en) * 2003-08-06 2009-01-27 Applied Materials, Inc. Chamber stability monitoring using an integrated metrology tool
JP4564272B2 (ja) 2004-03-23 2010-10-20 株式会社東芝 半導体装置およびその製造方法
US20080166854A1 (en) * 2005-09-09 2008-07-10 Dong-Suk Shin Semiconductor devices including trench isolation structures and methods of forming the same
KR100772704B1 (ko) * 2005-09-29 2007-11-02 주식회사 하이닉스반도체 테이퍼형태의 트렌치를 갖는 반도체소자의 제조 방법

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08203875A (ja) * 1995-01-27 1996-08-09 Fuji Electric Co Ltd ドライエッチングによる部品の製造方法
US5807784A (en) * 1995-05-30 1998-09-15 Samsung Electronics Co., Ltd. Device isolation methods for a semiconductor device
CN1064779C (zh) * 1996-01-11 2001-04-18 现代电子产业株式会社 半导体器件中的隔离方法
US6495294B1 (en) * 1999-10-28 2002-12-17 Denso Corporation Method for manufacturing semiconductor substrate having an epitaxial film in the trench
JP2003303817A (ja) * 2002-02-07 2003-10-24 Tokyo Electron Ltd エッチング方法
US20040014281A1 (en) * 2002-07-18 2004-01-22 Hynix Semiconductor Inc. Method of manufacturing flash memory device using trench device isolation process
US6576558B1 (en) * 2002-10-02 2003-06-10 Taiwan Semiconductor Manufacturing Company High aspect ratio shallow trench using silicon implanted oxide

Also Published As

Publication number Publication date
CN1674248A (zh) 2005-09-28
US20070082458A1 (en) 2007-04-12
US7781293B2 (en) 2010-08-24
KR100707899B1 (ko) 2007-04-16
KR20060044527A (ko) 2006-05-16
JP4564272B2 (ja) 2010-10-20
US20050221579A1 (en) 2005-10-06
JP2005276930A (ja) 2005-10-06

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Effective date of registration: 20170728

Address after: Tokyo, Japan

Patentee after: TOSHIBA MEMORY Corp.

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Patentee before: Toshiba Corp.

CP01 Change in the name or title of a patent holder

Address after: Tokyo

Patentee after: TOSHIBA MEMORY Corp.

Address before: Tokyo

Patentee before: Japanese businessman Panjaya Co.,Ltd.

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Patentee after: Kaixia Co.,Ltd.

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Patentee before: TOSHIBA MEMORY Corp.

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Effective date of registration: 20211119

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Patentee after: Japanese businessman Panjaya Co.,Ltd.

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Granted publication date: 20080326

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