JP4554930B2 - 材料を接合及び転写して半導体デバイスを形成する方法 - Google Patents

材料を接合及び転写して半導体デバイスを形成する方法 Download PDF

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Publication number
JP4554930B2
JP4554930B2 JP2003553615A JP2003553615A JP4554930B2 JP 4554930 B2 JP4554930 B2 JP 4554930B2 JP 2003553615 A JP2003553615 A JP 2003553615A JP 2003553615 A JP2003553615 A JP 2003553615A JP 4554930 B2 JP4554930 B2 JP 4554930B2
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substrate
donor
receiving
bulk
mesa
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Japanese (ja)
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JP2005513781A5 (https=
JP2005513781A (ja
Inventor
イー． ジョーンズ、ロバート
チュタク、セバスチャン
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NXP USA Inc
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NXP USA Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Element Separation (AREA)
  • Light Receiving Elements (AREA)
JP2003553615A 2001-12-17 2002-12-05 材料を接合及び転写して半導体デバイスを形成する方法 Expired - Fee Related JP4554930B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/022,711 US6616854B2 (en) 2001-12-17 2001-12-17 Method of bonding and transferring a material to form a semiconductor device
PCT/US2002/038564 WO2003052817A2 (en) 2001-12-17 2002-12-05 Method of bonding and transferring a material to form a semiconductor device

Publications (3)

Publication Number Publication Date
JP2005513781A JP2005513781A (ja) 2005-05-12
JP2005513781A5 JP2005513781A5 (https=) 2006-02-02
JP4554930B2 true JP4554930B2 (ja) 2010-09-29

Family

ID=21811041

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003553615A Expired - Fee Related JP4554930B2 (ja) 2001-12-17 2002-12-05 材料を接合及び転写して半導体デバイスを形成する方法

Country Status (8)

Country Link
US (1) US6616854B2 (https=)
EP (1) EP1500132A2 (https=)
JP (1) JP4554930B2 (https=)
KR (1) KR20040079916A (https=)
CN (1) CN1324674C (https=)
AU (1) AU2002353020A1 (https=)
TW (1) TWI255525B (https=)
WO (1) WO2003052817A2 (https=)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7078320B2 (en) * 2004-08-10 2006-07-18 International Business Machines Corporation Partial wafer bonding and dicing
US7288458B2 (en) * 2005-12-14 2007-10-30 Freescale Semiconductor, Inc. SOI active layer with different surface orientation
KR100755368B1 (ko) * 2006-01-10 2007-09-04 삼성전자주식회사 3차원 구조를 갖는 반도체 소자의 제조 방법들 및 그에의해 제조된 반도체 소자들
US7682930B2 (en) * 2006-06-09 2010-03-23 Aptina Imaging Corporation Method of forming elevated photosensor and resulting structure
US7432174B1 (en) * 2007-03-30 2008-10-07 Advanced Micro Devices, Inc. Methods for fabricating semiconductor substrates with silicon regions having differential crystallographic orientations
EP1993126B1 (en) * 2007-05-18 2011-09-21 Semiconductor Energy Laboratory Co., Ltd. Manufacturing methods of semiconductor substrate
US8201325B2 (en) 2007-11-22 2012-06-19 International Business Machines Corporation Method for producing an integrated device
US7842583B2 (en) * 2007-12-27 2010-11-30 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate and method for manufacturing semiconductor device
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
GB0914251D0 (en) * 2009-08-14 2009-09-30 Nat Univ Ireland Cork A hybrid substrate
CN102822970B (zh) * 2010-03-31 2015-06-17 Soitec公司 键合半导体结构及其形成方法
FR2965974B1 (fr) * 2010-10-12 2013-11-29 Soitec Silicon On Insulator Procédé de collage moléculaire de substrats en silicium et en verre
US8778737B2 (en) 2011-10-31 2014-07-15 International Business Machines Corporation Flattened substrate surface for substrate bonding
US9190379B2 (en) 2012-09-27 2015-11-17 Apple Inc. Perimeter trench sensor array package
US9209142B1 (en) * 2014-09-05 2015-12-08 Skorpios Technologies, Inc. Semiconductor bonding with compliant resin and utilizing hydrogen implantation for transfer-wafer removal
WO2017052646A1 (en) * 2015-09-25 2017-03-30 Intel Corporation Island transfer for optical, piezo and rf applications

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4966646A (en) 1986-09-24 1990-10-30 Board Of Trustees Of Leland Stanford University Method of making an integrated, microminiature electric-to-fluidic valve
US5389569A (en) * 1992-03-03 1995-02-14 Motorola, Inc. Vertical and lateral isolation for a semiconductor device
JP3114570B2 (ja) * 1995-05-26 2000-12-04 オムロン株式会社 静電容量型圧力センサ
JPH09127352A (ja) * 1995-10-30 1997-05-16 Hitachi Ltd 半導体装置およびその製造方法
JP3257624B2 (ja) * 1996-11-15 2002-02-18 キヤノン株式会社 半導体部材の製造方法
US6191007B1 (en) 1997-04-28 2001-02-20 Denso Corporation Method for manufacturing a semiconductor substrate
JPH1140823A (ja) * 1997-05-22 1999-02-12 Fujitsu Ltd 光検出器モジュール
JPH1145862A (ja) * 1997-07-24 1999-02-16 Denso Corp 半導体基板の製造方法
US6271101B1 (en) * 1998-07-29 2001-08-07 Semiconductor Energy Laboratory Co., Ltd. Process for production of SOI substrate and process for production of semiconductor device
US6093623A (en) 1998-08-04 2000-07-25 Micron Technology, Inc. Methods for making silicon-on-insulator structures
JP4313874B2 (ja) * 1999-02-02 2009-08-12 キヤノン株式会社 基板の製造方法
JP2001007362A (ja) * 1999-06-17 2001-01-12 Canon Inc 半導体基材および太陽電池の製造方法
JP2001102523A (ja) * 1999-09-28 2001-04-13 Sony Corp 薄膜デバイスおよびその製造方法
US6400009B1 (en) * 1999-10-15 2002-06-04 Lucent Technologies Inc. Hermatic firewall for MEMS packaging in flip-chip bonded geometry

Also Published As

Publication number Publication date
EP1500132A2 (en) 2005-01-26
WO2003052817A3 (en) 2003-08-21
WO2003052817A2 (en) 2003-06-26
US6616854B2 (en) 2003-09-09
CN1615543A (zh) 2005-05-11
US20030114001A1 (en) 2003-06-19
KR20040079916A (ko) 2004-09-16
CN1324674C (zh) 2007-07-04
TWI255525B (en) 2006-05-21
AU2002353020A8 (en) 2003-06-30
JP2005513781A (ja) 2005-05-12
AU2002353020A1 (en) 2003-06-30
WO2003052817B1 (en) 2003-09-25
TW200302548A (en) 2003-08-01

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