JP6141853B2 - 3d集積化プロセスにおいて材料の層を転写する方法ならびに関連する構造体およびデバイス - Google Patents
3d集積化プロセスにおいて材料の層を転写する方法ならびに関連する構造体およびデバイス Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Description
Claims (5)
- 半導体材料の層を第1のドナー構造体から第2の構造体に転写する方法であって、
前記第1のドナー構造体の主表面に凹部を形成するステップと、
前記凹部に誘電体材料を充填するステップと、
イオンを前記第1のドナー構造体中に注入して、前記注入されたイオンによって画定される前記第1のドナー構造体内の概して平面の脆弱化ゾーンを形成するするステップであり、前記概して平面の脆弱化ゾーンは、前記第1のドナー構造体の前記半導体材料の層を前記第1のドナー構造体の残りの部分から区切り、前記注入されたイオンの濃度および前記注入されたイオンの元素組成の少なくとも一方が、前記概して平面の脆弱化ゾーンに平行な少なくとも1つの方向に前記概して平面の脆弱化ゾーンの中で変化する、ステップと、
前記第1のドナー構造体を前記第2の構造体に接合するステップと、
前記第1のドナー構造体を前記概して平面の脆弱化ゾーンに沿って破断し、前記第2の構造体に接合された前記半導体材料の層を残すステップと、
を含み、前記イオンを前記第1のドナー構造体中に注入するステップは、前記第1のドナー構造体の前記主表面の非凹部の区域中にイオンを注入することなしに前記凹部内の前記誘電体材料を通して前記第1のドナー構造体中にイオンを注入するステップを含むことを特徴とする方法。 - 前記イオンを前記第1のドナー構造体中に注入するステップは、前記イオンを前記第1のドナー構造体中にパターン化マスクの開口を通して注入するステップを含むことを特徴とする請求項1に記載の方法。
- 半導体材料の層を第1のドナー構造体から第2の構造体に転写する方法であって、
前記第1のドナー構造体の主表面に凹部を形成するステップと、
前記第1のドナー構造体の主表面と前記凹部内の側壁表面および底部表面との上に第1の共形層を堆積させるステップと、
前記第1の共形層上に前記第1の共形層と異なる組成の第2の共形層を堆積させるステップと、
前記第2の共形層の前記凹部の側壁表面と平行な部分以外をエッチングするステップと、
前記第2の共形層で覆われていない、露出した前記第1の共形層のみをエッチングするステップと、
イオンを前記第1のドナー構造体中に注入して、前記注入されたイオンによって画定される前記第1のドナー構造体内の概して平面の脆弱化ゾーンを形成するするステップであり、前記概して平面の脆弱化ゾーンは、前記第1のドナー構造体の前記半導体材料の層を前記第1のドナー構造体の残りの部分から区切り、前記注入されたイオンの濃度および前記注入されたイオンの元素組成の少なくとも一方が、前記概して平面の脆弱化ゾーンに平行な少なくとも1つの方向に前記概して平面の脆弱化ゾーンの中で変化する、ステップと、
前記第1のドナー構造体を前記第2の構造体に接合するステップと、
前記第1のドナー構造体を前記概して平面の脆弱化ゾーンに沿って破断し、前記第2の構造体に接合された前記半導体材料の層を残すステップと、
を含み、前記イオンを前記第1のドナー構造体中に注入するステップは、前記第1のドナー構造体の前記主表面の非凹部の区域中にイオンを注入することなしに前記凹部の前記第1のドナー構造体が露出した底部を通して前記第1のドナー構造体中にイオンを注入するステップを含むことを特徴とする方法。 - 第1のドナー構造体であり、その中に概して平面の脆弱化ゾーンを有し、前記概して平面の脆弱化ゾーンは、前記概して平面の脆弱化ゾーンに沿った前記第1のドナー構造体内の注入されたイオンによって画定され、前記概して平面の脆弱化ゾーンは、前記第1のドナー構造体の半導体材料の層を前記第1のドナー構造体の残りの部分から区切り、前記注入されたイオンの濃度および前記注入されたイオンの元素組成の少なくとも一方が、前記概して平面の脆弱化ゾーンに平行な少なくとも1つの方向に前記概して平面の脆弱化ゾーンの中で変化する、第1のドナー構造体と、
前記第1のドナー構造体の主表面に形成された凹部と、
前記凹部に充填された誘電体材料と、
前記第1のドナー構造体の前記半導体材料の層に接合される第2の構造体と、を含み、前記凹部直下の前記概して平面の脆弱化ゾーン内の領域の前記イオンの濃度は、前記凹部の間の前記概して平面の脆弱化ゾーン内の領域の前記イオンの濃度よりも高いことを特徴とする半導体構造体。 - 第1のドナー構造体であり、その中に概して平面の脆弱化ゾーンを有し、前記概して平面の脆弱化ゾーンは、前記概して平面の脆弱化ゾーンに沿った前記第1のドナー構造体内の注入されたイオンによって画定され、前記概して平面の脆弱化ゾーンは、前記第1のドナー構造体の半導体材料の層を前記第1のドナー構造体の残りの部分から区切り、前記注入されたイオンの濃度および前記注入されたイオンの元素組成の少なくとも一方が、前記概して平面の脆弱化ゾーンに平行な少なくとも1つの方向に前記概して平面の脆弱化ゾーンの中で変化する、第1のドナー構造体と、
前記第1のドナー構造体の主表面に形成された凹部と、
前記凹部の側壁表面に堆積したスペーサ構造体と、
前記第1のドナー構造体の前記半導体材料の層に接合される第2の構造体と、
を含み、前記凹部直下の前記概して平面の脆弱化ゾーン内の領域の前記イオンの濃度は、前記凹部の間の前記概して平面の脆弱化ゾーン内の領域の前記イオンの濃度よりも高いことを特徴とする半導体構造体。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
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US13/246,580 US8673733B2 (en) | 2011-09-27 | 2011-09-27 | Methods of transferring layers of material in 3D integration processes and related structures and devices |
US13/246,580 | 2011-09-27 | ||
FR1159358 | 2011-10-17 | ||
FR1159358A FR2981501B1 (fr) | 2011-10-17 | 2011-10-17 | Procédé de transfert de couches matériau dans des processus d’intégration 3d et structures et dispositifs associes |
PCT/IB2012/001578 WO2013045985A1 (en) | 2011-09-27 | 2012-08-13 | Methods of transferring layers of material in 3d integration processes and related structures and devices |
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JP2014531768A JP2014531768A (ja) | 2014-11-27 |
JP6141853B2 true JP6141853B2 (ja) | 2017-06-07 |
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JP (1) | JP6141853B2 (ja) |
KR (1) | KR101955375B1 (ja) |
CN (1) | CN103828036B (ja) |
DE (1) | DE112012004024T5 (ja) |
TW (1) | TWI573198B (ja) |
WO (1) | WO2013045985A1 (ja) |
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US8984463B2 (en) | 2012-11-28 | 2015-03-17 | Qualcomm Incorporated | Data transfer across power domains |
US9536840B2 (en) | 2013-02-12 | 2017-01-03 | Qualcomm Incorporated | Three-dimensional (3-D) integrated circuits (3DICS) with graphene shield, and related components and methods |
US20140225218A1 (en) * | 2013-02-12 | 2014-08-14 | Qualcomm Incorporated | Ion reduced, ion cut-formed three-dimensional (3d) integrated circuits (ic) (3dics), and related methods and systems |
US9041448B2 (en) | 2013-03-05 | 2015-05-26 | Qualcomm Incorporated | Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC) (3DIC) and related methods |
US9177890B2 (en) | 2013-03-07 | 2015-11-03 | Qualcomm Incorporated | Monolithic three dimensional integration of semiconductor integrated circuits |
US9171608B2 (en) | 2013-03-15 | 2015-10-27 | Qualcomm Incorporated | Three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) tiers, and related 3D integrated circuits (3DICS), 3DIC processor cores, and methods |
FR3034569B1 (fr) * | 2015-04-02 | 2021-10-22 | Soitec Silicon On Insulator | Electrolyte solide avance et sa methode de fabrication |
FR3041364B1 (fr) * | 2015-09-18 | 2017-10-06 | Soitec Silicon On Insulator | Procede de transfert de paves monocristallins |
FR3073083B1 (fr) * | 2017-10-31 | 2019-10-11 | Soitec | Procede de fabrication d'un film sur un feuillet flexible |
FR3079659B1 (fr) | 2018-03-29 | 2020-03-13 | Soitec | Procede de fabrication d'un substrat donneur pour la realisation d'une structure integree en trois dimensions et procede de fabrication d'une telle structure integree |
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FR2748851B1 (fr) * | 1996-05-15 | 1998-08-07 | Commissariat Energie Atomique | Procede de realisation d'une couche mince de materiau semiconducteur |
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FR2755537B1 (fr) | 1996-11-05 | 1999-03-05 | Commissariat Energie Atomique | Procede de fabrication d'un film mince sur un support et structure ainsi obtenue |
FR2758907B1 (fr) * | 1997-01-27 | 1999-05-07 | Commissariat Energie Atomique | Procede d'obtention d'un film mince, notamment semiconducteur, comportant une zone protegee des ions, et impliquant une etape d'implantation ionique |
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- 2012-08-13 JP JP2014532486A patent/JP6141853B2/ja active Active
- 2012-08-13 CN CN201280046870.1A patent/CN103828036B/zh active Active
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DE112012004024T5 (de) | 2014-07-24 |
WO2013045985A1 (en) | 2013-04-04 |
CN103828036A (zh) | 2014-05-28 |
TW201330117A (zh) | 2013-07-16 |
CN103828036B (zh) | 2017-02-15 |
KR20140065435A (ko) | 2014-05-29 |
TWI573198B (zh) | 2017-03-01 |
JP2014531768A (ja) | 2014-11-27 |
KR101955375B1 (ko) | 2019-03-07 |
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