JP4338488B2 - デュアルまたはマルチプルゲートを使用するtftの設計方法 - Google Patents
デュアルまたはマルチプルゲートを使用するtftの設計方法 Download PDFInfo
- Publication number
- JP4338488B2 JP4338488B2 JP2003329609A JP2003329609A JP4338488B2 JP 4338488 B2 JP4338488 B2 JP 4338488B2 JP 2003329609 A JP2003329609 A JP 2003329609A JP 2003329609 A JP2003329609 A JP 2003329609A JP 4338488 B2 JP4338488 B2 JP 4338488B2
- Authority
- JP
- Japan
- Prior art keywords
- tft
- active channel
- dual
- primary
- channel region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000009977 dual effect Effects 0.000 title claims description 24
- 238000000034 method Methods 0.000 title claims description 18
- 239000013078 crystal Substances 0.000 claims description 72
- 239000000758 substrate Substances 0.000 claims description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 19
- 230000001360 synchronised effect Effects 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 description 23
- 239000011159 matrix material Substances 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 230000000694 effects Effects 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000002425 crystallisation Methods 0.000 description 7
- 239000002800 charge carrier Substances 0.000 description 5
- 230000008025 crystallization Effects 0.000 description 5
- 239000010409 thin film Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000002498 deadly effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
- H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
Description
したがって、P+Q=1で、P=(a+b)/Gsと定義する。
D=(L+x)×cosθで、x=W×tanθである。
D=(L+Wtanθ)×cosθ=Lcosθ+Wtanθcosθで、
tanθcosθ=sinθであるので、
つまり、D=Lcosθ+Wsinθである。
したがって、前記最大距離Dはアクティブチャンネル領域の長さLと幅W、そして法線Nに対する“プライマリー”結晶粒境界の傾いた角度θだけの関数で表すことができる。
Nmax=ξ(D/Gs)、
ここで、関数ξは次のように定義される。
ξ(x)=最小の整数≧x,x=任意の数である。
すなわち、xが2であればNmax=2であり、x=2.3であればNmax=3になる関数であることが分かる。
(数1)
P=(D−(Nmax−1)×Gs)/Gsで、
(数2)
Q=1−P=1−(D−(Nmax−1)×Gs/Gs)=(−D+Nmax×Gs)/Gsになる。
a)P=0の場合
アクティブチャンネル領域内にはNmax−1個の“プライマリー”結晶粒境界の最大数Nmaxが含まれる確率は0で、よって、アクティブチャンネル領域内にはNmax−1個の“プライマリー”結晶粒境界の数のみが存在できる。 b)0<P<0.5の場合
アクティブチャンネル領域内にNmax個の“プライマリー”結晶粒境界の数が存在する確率はNmax−1個の境界の数が存在する確率よりも低い。
c)P=0.5の場合
アクティブチャンネル領域内にNmax個の“プライマリー”結晶粒境界の数を含む確率がNmax−1個の境界の数を含む確率と同じである。
d)0.5<P<1の場合
アクティブチャンネル領域内にNmax個の“プライマリー”結晶粒境界の数を含む確率がNmax−1個の境界の数を含む確率と同じである。
e)P=1の場合
アクティブチャンネル領域内に“プライマリー”結晶粒境界の最大数Nmaxを含む確率は1で、よって、アクティブチャンネル領域内ではNmax個の“プライマリー”結晶粒境界の数のみが存在できる。
このとき、前記確率Pを表す式でD=Lになり(図4(A)、4(B))、前記Pはこれ以上W及びθの関数ではない。このとき、確率Pは次のように表すことができる。
P=(L−(Nmax−1)×Gs)/Gs
このとき、アクティブチャンネル領域内にNmax−1個の“プライマリー”結晶粒境界の数を含む確率QはP+Q=1であるので、
Q=1−P=1−(L−(Nmax−1)×Gs))/Gs=(−L+Nmax×Gs)/Gsである。
(数3)
S=mGs secθ−Lであり、
ここで、Gsは結晶粒の大きさ、mは1,2,3,・・・整数>0、θはアクティブチャンネル方向の垂直方向に対して致命的な結晶粒境界(“プライマリー”結晶粒境界)が傾く角度、Lはデュアルまたはマルチプルゲート各々のアクティブチャンネル長さである。
θ=0の場合、secθ=1で、
よって、S=mGs−Lで表現されることができる。
Claims (2)
- TFT基板上に多結晶シリコンの結晶粒が四角形状で規則的に成長したものとしてモデル化し、前記多結晶シリコンの結晶粒を利用して形成されたアクティブチャンネルを備えたデュアルまたはマルチプルゲートTFTの設計方法において、
前記TFT基板を形成する多結晶シリコンの結晶粒の大きさGsと、前記ゲートのアクティブチャンネル方向の垂直方向に対して“プライマリー”結晶粒境界が傾いた角度θと、前記デュアルまたはマルチプルゲートTFT各々のアクティブチャンネルの幅W及び長さLと、長さがL、幅がWの前記デュアルまたはマルチプルゲートTFT各々のアクティブチャンネル領域内に含まれる前記“プライマリー”結晶粒境界の最大数Nmaxとに基づいて、前記アクティブチャンネル領域内に前記‘プライマリー’結晶粒境界の最大数が含まれる確率Pを
P=(D−(Nmax−1)×Gs)/Gs
(ただし、D=Lcosθ+Wsinθ)
に基づいて計算する段階と、
前記確率Pの値が0.5とならないように調整し、前記デュアルまたはマルチプルゲートTFTの各アクティブチャンネル領域内に含まれる前記“プライマリー”結晶粒境界の数を同期化できるアクティブチャンネル間の間隔Sを
S=mGs secθ−L
(ただし、mは1,2,3,・・・整数>0)
に基づいて調整する段階と、
を含んでいることを特徴とするデュアルまたはマルチプルゲートを使用するTFTの設計方法。 - 前記角度θは−45゜≦θ≦45゜であることを特徴とする、請求項1に記載のデュアルまたはマルチプルゲートを使用するTFTの設計方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2002-0064366A KR100454751B1 (ko) | 2002-10-21 | 2002-10-21 | 듀얼 또는 멀티플 게이트를 사용하는 티에프티의 제조 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004146809A JP2004146809A (ja) | 2004-05-20 |
JP4338488B2 true JP4338488B2 (ja) | 2009-10-07 |
Family
ID=36461428
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003329609A Expired - Fee Related JP4338488B2 (ja) | 2002-10-21 | 2003-09-22 | デュアルまたはマルチプルゲートを使用するtftの設計方法 |
Country Status (5)
Country | Link |
---|---|
US (2) | US7011992B2 (ja) |
EP (1) | EP1414062A3 (ja) |
JP (1) | JP4338488B2 (ja) |
KR (1) | KR100454751B1 (ja) |
CN (1) | CN100361283C (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1324540C (zh) * | 2003-06-05 | 2007-07-04 | 三星Sdi株式会社 | 具有多晶硅薄膜晶体管的平板显示装置 |
WO2006007757A1 (en) * | 2004-07-16 | 2006-01-26 | Quanta Display Inc. | A low temperature poly-silicon thin film transistor |
KR100731752B1 (ko) * | 2005-09-07 | 2007-06-22 | 삼성에스디아이 주식회사 | 박막트랜지스터 |
JP4996846B2 (ja) * | 2005-11-22 | 2012-08-08 | 株式会社日立製作所 | 電界効果トランジスタ及びその製造方法 |
CN101681930B (zh) * | 2007-06-22 | 2012-11-14 | 香港科技大学 | 具有搭桥晶粒结构的多晶硅薄膜晶体管 |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN2038669U (zh) * | 1988-12-15 | 1989-05-31 | 中国科学院半导体研究所 | 双栅mos器件 |
GB9606083D0 (en) | 1996-03-22 | 1996-05-22 | Philips Electronics Nv | Electronic device manufacture |
US6555449B1 (en) * | 1996-05-28 | 2003-04-29 | Trustees Of Columbia University In The City Of New York | Methods for producing uniform large-grained and grain boundary location manipulated polycrystalline thin film semiconductors using sequential lateral solidfication |
WO1997045827A1 (en) | 1996-05-28 | 1997-12-04 | The Trustees Of Columbia University In The City Of New York | Crystallization processing of semiconductor film regions on a substrate, and devices made therewith |
US5981974A (en) * | 1996-09-30 | 1999-11-09 | Sharp Kabushiki Kaisha | Semiconductor device and method for fabricating the same |
KR100500033B1 (ko) * | 1996-10-15 | 2005-09-08 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체장치 |
KR100244967B1 (ko) * | 1996-12-26 | 2000-02-15 | 김영환 | 듀얼 게이트(dual-gate)의 반도체 장치 제조방법 |
JP3274081B2 (ja) * | 1997-04-08 | 2002-04-15 | 松下電器産業株式会社 | 薄膜トランジスタの製造方法および液晶表示装置の製造方法 |
KR100292048B1 (ko) * | 1998-06-09 | 2001-07-12 | 구본준, 론 위라하디락사 | 박막트랜지스터액정표시장치의제조방법 |
JP2000243968A (ja) * | 1999-02-24 | 2000-09-08 | Matsushita Electric Ind Co Ltd | 薄膜トランジスタとその製造方法及びそれを用いた液晶表示装置とその製造方法 |
JP4307635B2 (ja) * | 1999-06-22 | 2009-08-05 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
KR100303142B1 (ko) * | 1999-10-29 | 2001-11-02 | 구본준, 론 위라하디락사 | 액정표시패널의 제조방법 |
FR2801396B1 (fr) * | 1999-11-22 | 2002-11-08 | Canon Kk | Convertion en mode point de donnees numeriques |
KR100660814B1 (ko) * | 1999-12-31 | 2006-12-26 | 엘지.필립스 엘시디 주식회사 | 박막트랜지스터의 반도체층 형성방법 |
JP2001345454A (ja) | 2000-03-27 | 2001-12-14 | Semiconductor Energy Lab Co Ltd | 半導体装置およびその作製方法 |
JP2001345451A (ja) * | 2000-05-30 | 2001-12-14 | Hitachi Ltd | 薄膜半導体集積回路装置、それを用いた画像表示装置、及びその製造方法 |
US6602765B2 (en) * | 2000-06-12 | 2003-08-05 | Seiko Epson Corporation | Fabrication method of thin-film semiconductor device |
JP2002246608A (ja) | 2000-11-09 | 2002-08-30 | Semiconductor Energy Lab Co Ltd | 半導体装置 |
KR100483985B1 (ko) * | 2001-11-27 | 2005-04-15 | 삼성에스디아이 주식회사 | 박막 트랜지스터용 다결정 실리콘 박막 및 이를 사용한디바이스 |
KR100462862B1 (ko) | 2002-01-18 | 2004-12-17 | 삼성에스디아이 주식회사 | 티에프티용 다결정 실리콘 박막 및 이를 이용한디스플레이 디바이스 |
KR100483987B1 (ko) * | 2002-07-08 | 2005-04-15 | 삼성에스디아이 주식회사 | 티에프티용 다결정 실리콘 박막 및 이를 사용한 디바이스 |
-
2002
- 2002-10-21 KR KR10-2002-0064366A patent/KR100454751B1/ko active IP Right Grant
-
2003
- 2003-09-22 JP JP2003329609A patent/JP4338488B2/ja not_active Expired - Fee Related
- 2003-10-03 US US10/677,278 patent/US7011992B2/en not_active Expired - Lifetime
- 2003-10-17 CN CNB2003101024062A patent/CN100361283C/zh not_active Expired - Lifetime
- 2003-10-21 EP EP03090360A patent/EP1414062A3/en not_active Withdrawn
-
2006
- 2006-01-11 US US11/329,030 patent/US7482179B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
EP1414062A2 (en) | 2004-04-28 |
KR20040034270A (ko) | 2004-04-28 |
US20040077132A1 (en) | 2004-04-22 |
KR100454751B1 (ko) | 2004-11-03 |
CN100361283C (zh) | 2008-01-09 |
US7011992B2 (en) | 2006-03-14 |
EP1414062A3 (en) | 2008-04-23 |
US7482179B2 (en) | 2009-01-27 |
CN1497685A (zh) | 2004-05-19 |
US20060110864A1 (en) | 2006-05-25 |
JP2004146809A (ja) | 2004-05-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4361722B2 (ja) | Tft用多結晶シリコン薄膜の設計方法及びこれを用いて作製されたtftを備えたデバイス | |
US8987120B2 (en) | Flat panel display device comprising polysilicon thin film transistor and method of manufacturing the same | |
JP4361740B2 (ja) | Tft用多結晶シリコン薄膜の設計方法及びこれを用いて作製されたtftを備えたディスプレーデバイス | |
US7109075B2 (en) | Method for fabrication of polycrystallin silicon thin film transistors | |
JP4338488B2 (ja) | デュアルまたはマルチプルゲートを使用するtftの設計方法 | |
JP5069842B2 (ja) | 薄膜トランジスタ | |
JP4338463B2 (ja) | Tft用多結晶シリコン薄膜の設計方法及びこれを使用して形成されたデバイス | |
KR100552958B1 (ko) | 다결정 실리콘 박막 트랜지스터를 포함하는 평판 표시소자 및 그의 제조 방법 | |
JP4361769B2 (ja) | Ldd/オフセット構造を具備している薄膜トランジスター | |
KR100534577B1 (ko) | 특성이 우수한 디스플레이 디바이스 | |
CN109509757B (zh) | 液晶显示器Demux结构、制作方法及液晶显示器 | |
JP2004172569A (ja) | 均一性に優れた薄膜トランジスタ及びこれを用いる有機電界発光素子 | |
US20040163585A1 (en) | Method for manufacturing polycrystalline silicon thin film and thin film transistor fabricated using polycrystalline silicon thin film manufactured by the manufacturing | |
US20170133516A1 (en) | Array substrate and method for manufacturing the array substrate and display panel | |
KR100534576B1 (ko) | 다중 게이트를 갖는 박막 트랜지스터 | |
KR100542992B1 (ko) | 다결정 실리콘 박막 트랜지스터를 포함하는 평판 표시 소자 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20050119 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20070123 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20070306 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20070531 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20080805 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20081104 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20081205 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20090331 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20090616 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20090630 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4338488 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120710 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130710 Year of fee payment: 4 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130710 Year of fee payment: 4 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130710 Year of fee payment: 4 |
|
R360 | Written notification for declining of transfer of rights |
Free format text: JAPANESE INTERMEDIATE CODE: R360 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130710 Year of fee payment: 4 |
|
R360 | Written notification for declining of transfer of rights |
Free format text: JAPANESE INTERMEDIATE CODE: R360 |
|
R371 | Transfer withdrawn |
Free format text: JAPANESE INTERMEDIATE CODE: R371 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130710 Year of fee payment: 4 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130710 Year of fee payment: 4 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |