WO2006007757A1

WO2006007757A1 - A low temperature poly-silicon thin film transistor

Info

Publication number: WO2006007757A1
Application number: PCT/CN2004/000822
Authority: WO
Inventors: Zhengzhang Guo
Original assignee: Quanta Display Inc.; Quanta Display Japan Inc.
Priority date: 2004-07-16
Filing date: 2004-07-16
Publication date: 2006-01-26

Abstract

A low temperature poly-silicon thin film transistor is mainly comprised of a top-cover layer, a poly-silicon thin film and a gate electrode. Wherein the top-cover layer is arranged on the substrate , and has a hollow space between them. The poly-silicon thin film is arranged on the top-cover layer, and divided with a channel region and source/drain region at the both sides of the channel region. Wherein the channel region is placed on the top of the hollow space. Othewise, the gate electrode is arranged on the top of the channel region. Since the hollow space is placed on the channel region,when a laser annealing process is performed, the heat conductivity of this region is lower, silicon atom of the region has longer re-crystallization time, so that larger size of the grain has been formed, and grain boundary in the channel region is reduced. The grain orientation of the poly-silicon film is parcelled to the transmission direction of electron in the poly-silicon thin film transistor, so that the operation effect of the poly-silicon thin film transistor can be improved.

Description

Low-temperature polysilicon thin film transistor and method for manufacturing the same

The invention relates to a method for manufacturing a thin film transistor and a channel layer thereof, and particularly to a method for manufacturing a low temperature poly-silicon (LTPS) transistor and a channel layer thereof. Background technique

In general components, switches are required to drive the operation of the components. Taking an actively driven display element as an example, it is usually a Thin Film Transistor (TFT) as a driving switch. The thin film transistor can be divided into amorphous silicon (abbreviated as a-Si) thin film transistor and polycrystalline silicon (poly-silicon) thin film transistor according to the material of the channel region, because the polycrystalline silicon thin film transistor consumes compared with the amorphous silicon thin film transistor. The power is small and the electron mobility is large, so it is gradually receiving attention from the market.

Early polysilicon thin film transistors have process temperatures as high as 1000 degrees Celsius, so the choice of substrate quality is greatly limited. However, due to the development of laser technology, the process temperature can be reduced to below 600 degrees Celsius, and the polysilicon thin film transistor formed by such a process is also called a low temperature polysilicon thin film transistor.

In the low-temperature polysilicon thin film transistor, the polycrystalline silicon thin film is formed by first forming an amorphous silicon thin film on the substrate, and then melting (melting) the amorphous silicon thin film to become a polycrystalline silicon thin film. 1A and 1B are schematic cross-sectional views showing a manufacturing process of a conventional low-temperature polysilicon film. A commonly used laser annealing process is an Excimer Laser Annealing (ELA) process. Referring to FIG. 1A, after the amorphous silicon film 102 is formed on the substrate 100, the excimer laser beam 106 is used. A laser annealing process is performed to melt the amorphous silicon film 102 to recrystallize the silicon molecules into the polysilicon film 102a, as shown in FIG.

However, since the grain size of the polysilicon film 102a formed by the ELA process is too small and the uniformity of the uniformity is poor, there are many grain boundaries in the polysilicon film 102a, so that the electrons are in the polysilicon film. The mobility in the channel region of 102a is only about 100 to 200 cm-sec, which has a considerable influence on the performance of the thin film transistor.

In order to solve the above problems, another laser annealing process called Sequential Lateral Solidification (SLS) has been proposed. 2A to 2B are schematic cross-sectional views showing a manufacturing process of another conventional low-temperature polysilicon film.

Referring to FIG. 2A, the SLS process utilizes a mask 104 to define a range in which the amorphous silicon film 102 is irradiated by the laser beam 106 to melt the amorphous silicon film 102 in the partial region, that is, the amorphous silicon film 102 in the region 110. In some SLS processes, the reticle 104 is controlled by the machine to translate so that the laser beam passes through the holes 108 in the reticle 104 to illuminate all of the amorphous silicon film 102 in the region 110.

Referring to FIG. 2B, after a period of time, the molten amorphous silicon film 102 (that is, the amorphous silicon film 102 in the region 110) will grow laterally with the unmelted amorphous silicon film 102 as a crystal nucleus. Further, a polysilicon film 202a is formed in the region 110.

As can be seen from Fig. 2B, the SLS process can form a polysilicon film 202a having a large grain size. In other words, the grain boundary in the polysilicon film 202a formed by the SLS process is small, so the SLS process can improve the mobility of electrons in the polysilicon film and improve the efficiency of the thin film transistor compared with the conventional ELA process. The grain orientation of the polysilicon film is more uniform.

However, because the instrumentation equipment used in the SLS process is relatively expensive and it uses a special mask more than the conventional ELA process, the overall transistor is costly to manufacture. This In addition, the SLS process still cannot reduce the man-hour invention required to form a polysilicon film.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a low temperature polysilicon thin film transistor in which the crystal grains in the channel layer have better dimensional uniformity and less grain boundaries, so that the transistor has better element characteristics.

Another object of the present invention is to provide a method for fabricating a channel layer of a low temperature polysilicon thin film transistor which can control the grain size and crystal orientation in the channel region of the transistor, thereby increasing the mobility of electrons therein. In addition, the manufacturing equipment used in this manufacturing method can be compatible with existing manufacturing equipment, thereby saving manufacturing costs.

The present invention provides a low temperature polysilicon thin film transistor suitable for being disposed on a substrate. The low temperature polysilicon thin film transistor is mainly composed of a cap layer, a polysilicon film, and a gate. The top cover layer is disposed above the substrate and has a gap region between the substrate and the substrate. The polysilicon film is disposed on the cap layer and can be divided into a channel region and source/drain regions on both sides of the channel region. The channel region is located above the gap region, and the polysilicon film in the channel region is the channel layer of the transistor. The gate is placed above the channel area.

According to an embodiment of the invention, the CMOS transistor further includes a buffer layer disposed on the substrate between the cap layer and the substrate to block undesired diffusion of impurities in the substrate during the process. This in turn affects the performance of the component. In the present embodiment, the gap region is located, for example, between the cap layer and the buffer layer, and the gap region has a thermal conductivity lower than that of the buffer layer and the substrate.

According to an embodiment of the invention, the OLED film is further provided with a gate dielectric layer disposed on the polysilicon film.

According to an embodiment of the invention, the grains of the polysilicon film in the channel region are, for example, larger than the grains of the polysilicon film in the source/drain regions, thereby causing the transistor to have a higher driving current. And lower leakage current. In addition, since the grain size in the channel region is large, the number of grain interfaces therein is less than the number of grain interfaces in the source/drain regions, so electrons can be moved by the electric field in the channel region but are not easy. It is scattered by the grain interface, so it has better electron mobility. The width of the gate is preferably smaller than the size of the grains in the channel region. In addition, in another embodiment, the gate is, for example, a double-noisy structure, which further reduces the influence of electrons directly on the unique grain interface in the center of the channel, thereby significantly improving the performance of the transistor.

According to an embodiment of the invention, the CMOS transistor further includes a dielectric layer, a source/drain contact hole, and a source/drain conductor layer. Wherein, the dielectric layer is disposed on the polysilicon film and covers the gate. The source/drain contact holes are disposed in the dielectric layer and the gate dielectric layer and are in electrical contact with the source/drain regions. The source/drain conductor layer is disposed on the dielectric layer and filled in the source/drain contact holes to be electrically connected to the source/drain regions.

The present invention also provides a method for fabricating a channel layer of a low temperature polysilicon thin film transistor. The method first forms a sacrificial layer over the substrate, and sequentially forms a cap layer and an amorphous silicon film on the sacrificial layer. The sacrificial layer is then removed to form a gap region between the substrate and the cap layer. Thereafter, the amorphous silicon film is melted and then recrystallized to form a polysilicon channel layer on the cap layer above the gap region.

According to an embodiment of the invention, the method further includes forming a buffer layer on the substrate to prevent unintended diffusion of impurities in the substrate during the process before forming the sacrificial layer. The sacrificial layer is then formed on the buffer layer.

According to an embodiment of the present invention, the method of removing the sacrificial layer is, for example, a wet etching process which immerses the formed structure in an etchant, for example. In this step, the etch rate of the sacrificial layer is greater than the etch rate of the other layers.

According to an embodiment of the invention, the step of melting the amorphous silicon film and recrystallizing to form the polysilicon channel layer comprises first irradiating the amorphous silicon film with an excimer laser to melt the amorphous silicon film into a liquid silicon material. An annealing process is then performed to rearrange the grains in the silicon material A polysilicon film is formed. The polysilicon film located above the gap region is a polysilicon channel layer, and the silicon grains in the polysilicon channel layer are larger than the silicon grains in the polysilicon film in other regions.

The crystal orientation of the crystal grains in the polycrystalline silicon film formed by the present invention is parallel to the direction of electron transport of the subsequent transistor in the operating state, thereby improving the mobility of electrons in the channel region, thereby improving the operational efficiency of the transistor.

The above and other objects, features and advantages of the present invention will become more <RTIgt; DRAWINGS

1A and 1B are schematic cross-sectional views showing a manufacturing process of a conventional low-temperature polysilicon film. 2A to 2B are schematic cross-sectional views showing a manufacturing process of another conventional low-temperature polysilicon film.

3 is a cross-sectional view showing a low temperature polysilicon thin film transistor in accordance with a preferred embodiment of the present invention.

Fig. 4A is a top plan view showing a low temperature polysilicon thin film transistor in an embodiment of the present invention.

Fig. 4B is a top view of a low temperature polysilicon thin film transistor in another embodiment of the present invention.

5A to 5E are cross-sectional views showing the manufacturing process of a channel layer of a low-temperature polysilicon thin film transistor according to a preferred embodiment of the present invention.

6A to 6D show upper views thereof corresponding to Figs. 5A to 5E, respectively. detailed description

The invention removes amorphous silicon before converting the amorphous silicon film into a polycrystalline silicon film. In the subsequent process, the thin film is formed as a sacrificial layer under the region of the polysilicon channel to form a gap region with low thermal conductivity on both sides, so that the crystallization rate of the silicon crystal grains above is higher than that of the silicon crystal grains in the two regions. The rate is slow, which in turn causes the grains to grow laterally from both sides toward the center and grow into larger sized grains in the channel region. The following examples are presented to illustrate the principles of the invention and are to be understood by those skilled in the art.

3 is a cross-sectional view showing a low temperature polysilicon thin film transistor in accordance with a preferred embodiment of the present invention. Referring to FIG. 3, the low temperature polysilicon thin film transistor 330 of the present invention is mainly composed of a substrate 300, a cap layer 306, a polysilicon film 308a, a gate 316, and a source/drain conductor layer 336. The top cover layer 306 is disposed above the substrate 300, and in the embodiment, a buffer layer 302 between the top cover layer 306 and the substrate 300 is disposed on the substrate 300 to block impurities in the substrate. Unexpected diffusion occurs, which in turn affects the performance of the component.

In particular, there is a gap region 310 between the top cover layer 306 and the buffer layer 302. The gap region 310 has, for example, air or other gas having a low heat transfer coefficient.

The polysilicon film 308a is disposed on the cap layer 306, and can be divided into a channel region 322 and a source/drain region 318 doped with a dopant. The channel region 322 is located above the gap region 310, and the channel region The polysilicon film 308a in 322 is the polysilicon channel layer of the low temperature polysilicon thin film transistor 330. The gate 316 is disposed above the channel region 322 of the polysilicon film 308a, and the gate dielectric layer 314 is disposed, for example, on the polysilicon film 308a.

Dielectric layer 324 is disposed over gate dielectric layer 314 and covers gate 316. The source/drain conductor layer 336 is disposed on the dielectric layer 324, and the source/drain conductor layer 336 is disposed through the source/drain contact holes 332 disposed in the dielectric layer 324 and the gate dielectric layer 314. Electrically coupled to source/drain regions 318.

It is to be noted that, in this embodiment, the silicon grains 340 in the polysilicon film 308a in the channel region 322 are, for example, larger than the silicon grains 350 in the polysilicon film 308a in the source/drain regions 318, and The preferred size is approximately half the length L of the channel region 322, so the temperature is much lower The crystalline silicon thin film transistor 330 can have a higher driving current. Moreover, because the die 340 within the channel region 322 is relatively large, the number of die interfaces 360 within the channel region 322 may be less than the number of die interfaces 360 within the source/drain regions 318. And the crystal orientation of the crystal grains is parallel to the transmission direction of the electrons in the low temperature polysilicon thin film transistor 330, so when the low temperature polysilicon thin film transistor 330 is in operation, the electron carrier can easily pass through the channel region 322 without being affected by the channel region. The grain boundary 360 in 322 is excessively scattered and scatters, resulting in a decrease in electron mobility.

In particular, the present invention can also reduce the width of the gate 316 of the low temperature polysilicon thin film transistor 330 to be smaller than the size of the die 340 (as shown in FIG. 4A), thereby avoiding the channel region of the thin film transistor crossing the grain interface. In turn, the thin film transistor can have better performance. It will be appreciated by those skilled in the art that the so-called grain size herein generally refers to the length of the grain parallel to the width of the gate.

In addition to reducing the width of the gate, the present invention can also configure a dual gate structure 416 on the low temperature polysilicon thin film transistor, as shown in FIG. 4B, which shows a low temperature polysilicon thin film transistor in another embodiment of the present invention. Upper view. This dual gate structure 416 also reduces electrons directly from the unique grain interface in the center of the channel, thereby significantly improving transistor efficiency.

The present invention accomplishes a low temperature polycrystalline silicon thin film transistor having better characteristics in the above-described channel region by a special process, and a method of manufacturing the channel layer of the above low temperature polysilicon thin film transistor will be described below by way of an embodiment.

5A to 5E are cross-sectional views showing the manufacturing process of a channel layer of a low-temperature polysilicon thin film transistor according to a preferred embodiment of the present invention. 6A to 6D show their upper views corresponding to Figs. 5A to 5E, respectively.

Referring to FIG. 5A, a buffer layer 302 and a sacrificial layer 304 are formed on the substrate 300 in sequence, for example, by chemical vapor deposition (deposition) or sputtering (sputtering). The material of the layer 304 is, for example, metal. Material. It should be noted that the buffer layer 302 is an optional component, and its function is as described in the foregoing embodiment, and details are not described herein again. Those skilled in the art can determine the presence or absence of the buffer layer 302 according to the actual process requirements, which is not limited by the present invention. The sacrificial layer 304 is, for example, a rectangular patterned film layer disposed on the buffer layer 302, as shown in FIG. 6A.

Referring to FIG. 5B and FIG. 6B, a cap layer 306 and an amorphous silicon film 308 are sequentially formed on the buffer layer 302, and the sacrificial layer 304 is covered. Wherein, in a subsequent process, a channel layer of a low temperature polysilicon thin film transistor is formed in a region 312 above the sacrificial layer 304, and source/drain regions are formed in both sides of the region 312. Therefore, the width of the sacrificial layer 304 determines the length of the channel layer of the low temperature polysilicon thin film transistor. In other words, the length of the channel region in the low temperature polysilicon thin film transistor can be effectively controlled by controlling the width of the sacrificial layer 304.

Referring to FIG. 5C and FIG. 6C, the sacrificial layer 304 is then removed to form a gap region 310 between the cap layer 306 and the buffer layer 302, and the gap region 310 has, for example, air. This step is performed, for example, by removing the sacrificial layer 304 by wet etching, that is, immersing the structure illustrated in FIG. 5B in an etchant (not shown), and the etch rate of the etchant to the sacrificial layer 304 is large. The etch rate of the other layers is so that this step can remove the sacrificial layer 304 while the other layers remain intact.

Referring to FIG. 5D and FIG. 5E simultaneously, after the gap region 310 is formed, a laser annealing process is performed to melt the amorphous silicon film 308 and then recrystallize to form a polysilicon film 308a on the cap layer 306 above the gap region 310. A polysilicon channel layer 522 (i.e., a polysilicon film 308a located within region 312) is formed. The laser annealing process used in this embodiment is, for example, an excimer laser annealing process, as shown in FIG. 5D, which irradiates the amorphous silicon film 308 with an excimer laser beam 326 to melt it into liquid silicon (not shown). Out). After a period of time, the liquid silicon slowly cools down and recrystallizes into a polysilicon film. At this time, since the region 312 is located above the gap region 310, and the gap region 310 has, for example, air, and the heat conductivity of the air is about 0.025 W/cm K:, much smaller than the heat conduction of the cap layer 306 and the buffer layer 302. Coefficient. Therefore, the liquid crystallization rate in the region 312 is slower than that of the liquid silicon on both sides. In other words, during the curing process, the silicon atoms will grow from the sides to the center of the region 312 to form a polysilicon film 308a, and the polysilicon film 308a in the region 312 is the polysilicon channel layer 522 of the transistor, as shown in FIG. 5E and FIG. 6D. Show.

In particular, since the grain growth in the region 312 is slow, the grain size formed is larger than that formed in the both regions, that is, the crystal grains in the polysilicon channel layer 522 have a larger size. The size, for example, is slightly larger than half the length L of the polysilicon channel layer 322.

In addition, since the number of grain boundaries in the polysilicon channel layer 322 is less than the number of grain interfaces in the side regions, electrons can have better mobility in the polysilicon channel layer 322, thereby improving the operational efficiency of the transistor.

In summary, the low temperature polysilicon thin film transistor of the present invention has the following advantages -

1. Since the crystal grains in the channel region of the transistor have a large size and a preferable size uniformity, the transistor of the present invention has a high driving current and a high electron mobility.

2. The polycrystalline silicon thin film formed by the process of the present invention, wherein the crystal orientation of the crystal grains is parallel to the transport direction of electrons in the transistor, so the present invention can improve the mobility of electrons in the channel region, thereby improving the operational efficiency of the transistor. .

3. The width and length of the channel region in this transistor depends on the width and length of the sacrificial layer. Therefore, the width-to-length ratio of the channel region can adjust the size of the sacrificial layer according to the actual process, and the process margin is large.

4. The manufacturing apparatus of the present invention is compatible with existing manufacturing equipment, for example, the apparatus of the existing excimer laser annealing process can be used to achieve the level of the Sequential Lateral Solidification (SLS) process, that is, the present The invention can also save the cost of the process equipment while improving the quality of the product, so as to achieve the maximum production profit.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and any one skilled in the art can make some changes without departing from the spirit and scope of the invention. The invention is intended to be in the scope of the appended claims. Description of the reference numerals

100, 300: substrate

102, 308: amorphous silicon film

102a, 202a, 308a: polysilicon film

104: Photomask

106, 326: Excimer laser beam

108: Hole

110, 312: area

302: buffer layer

304: sacrificial layer

306: Top cover

310: gap area

314: Gate dielectric layer

316: Gate

318: source/drain regions

322: channel area

324: Dielectric layer

330: Low temperature polysilicon thin film transistor

332: source/drain contact hole

336: source/drain conductor layer

340, 350: silicon grains

416: Double gate structure

522: Polysilicon channel layer

Claims

Rights request

A low temperature polysilicon thin film transistor adapted to be disposed on a substrate, wherein the low temperature polysilicon thin film transistor comprises:

a cap layer disposed above the substrate, wherein the cap layer and the substrate have a gap region;

a polysilicon film disposed on the cap layer, the polysilicon film including a channel region and a source/drain region on both sides of the channel region, wherein the channel region is above the gap region;

a gate disposed over the channel region of the polysilicon film.

2 . The LTPS transistor of claim 1 , further comprising a buffer layer disposed between the substrate and the cap layer, wherein the gap region is located in the cap layer and the buffer layer between.

The low temperature polysilicon thin film transistor according to claim 2, wherein the gap region has a heat transfer coefficient lower than a heat transfer coefficient of the buffer layer.

The low temperature polysilicon thin film transistor according to claim 1, wherein the gap region has a heat transfer coefficient lower than a heat transfer coefficient of the substrate.

The low temperature polysilicon thin film transistor according to claim 1, further comprising a gate dielectric layer disposed on the polysilicon film.

The low temperature polysilicon thin film transistor according to claim 1, wherein a grain size in the channel region of the polysilicon film is larger than a grain size in the source/drain region of the polysilicon film.

The low temperature polysilicon thin film transistor according to claim 1, wherein the gate width is smaller than a grain size in the channel region.

8. The low temperature polysilicon thin film transistor according to claim 1, wherein Extremely a double gate structure.

The low temperature polysilicon thin film transistor of claim 1 , further comprising: a dielectric layer disposed on the polysilicon film and the gate, wherein the dielectric layer has a plurality of contact holes, Exposing the source/drain regions of the polysilicon film;

a source/drain conductor layer disposed on the dielectric layer, and the source/drain conductor layer is electrically connected to the source/drain regions of the polysilicon film through the contact holes in the dielectric layer connection.

A method of fabricating a channel layer of a low temperature polysilicon thin film transistor, characterized in that it comprises:

Forming a sacrificial layer over a substrate;

Forming a cap layer over the substrate to cover the sacrificial layer;

Forming an amorphous silicon film on the cap layer;

Removing the sacrificial layer to form a gap region between the substrate and the cap layer; and recrystallizing the amorphous silicon film to form a polysilicon channel on the cap layer above the gap region Floor.

11. The method of fabricating a channel layer of a low temperature polysilicon thin film transistor according to claim 10, further comprising forming a buffer layer on the substrate before forming the sacrificial layer over the substrate.

12. The method of fabricating a channel layer of a low temperature polysilicon thin film transistor according to claim 10, wherein the method of removing the sacrificial layer comprises wet etching, and an etch rate of the sacrificial layer is higher than that of the cap layer. Etched rate.

The method of fabricating a channel layer of a low temperature polysilicon thin film transistor according to claim 10, wherein the method of melting the amorphous silicon film comprises an excimer laser annealing process.