CN2717022Y - Low-temperature polysilicon thin-film transistor - Google Patents
Low-temperature polysilicon thin-film transistor Download PDFInfo
- Publication number
- CN2717022Y CN2717022Y CN 200420073977 CN200420073977U CN2717022Y CN 2717022 Y CN2717022 Y CN 2717022Y CN 200420073977 CN200420073977 CN 200420073977 CN 200420073977 U CN200420073977 U CN 200420073977U CN 2717022 Y CN2717022 Y CN 2717022Y
- Authority
- CN
- China
- Prior art keywords
- low
- film transistor
- temperature polysilicon
- zone
- polysilicon film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Thin Film Transistor (AREA)
Abstract
A low-temperature polysilicon thin-film transistor mainly comprises a cover layer, a polysilicon thin film and a gate electrode. Wherein, the cover layer is arranged on a base plate, an interval zone exists between the cover layer and the base plate, the polysilicon thin-film is arranged on the cover layer and is divided into a path zone and a source/ drain zone which is arranged at the two sides of the path zone, and wherein, the path zone is arranged on the interval zone, and the gate electrode is arranged on the path zone. Owing to the interval zone below the path zone, the thermal conductivity of the path zone is low when the laser annealing process is being carried on, so the silicon atom is provided with long recryst time in order to form a grain with large dimension, and therefore, the crystal interface in the path zone is reduced. The orientation of the grains in the polysilicon thin film is parallel to the transmission direction of the electron in the transistor, so the working capacity of the transistor can be increased.
Description
Technical field
The utility model relates to a kind of thin-film transistor, and is particularly related to a kind of low-temperature polysilicon film (low temperature poly-silicon abbreviates LTPS as) transistor.
Background technology
In general element, all need the running of deploy switch with driving element.Display element with active driving is an example, and normally (Thin Film Transistor is TFT) as driving switch with thin-film transistor for it.And thin-film transistor can be divided into amorphous silicon (amorphoussilicon according to the material of channel region, be called for short a-Si) thin-film transistor and polysilicon (poly-silicon) thin-film transistor, because polycrystalline SiTFT is little and electron mobility is big compared to its consumed power of amorphous silicon film transistor, therefore be subjected to the attention in market gradually.
The process temperatures of early stage polycrystalline SiTFT is up to 1000 degree Celsius, so the selection of substrate material is subjected to significantly limiting.But, recently because the development of laser technology, process temperatures can be reduced to below 600 degree Celsius, and utilizes the formed polycrystalline SiTFT of this kind processing procedure low-temperature polysilicon film transistor that is otherwise known as.
In low-temperature polysilicon film transistor, the formation method of polysilicon membrane is earlier to form amorphous silicon membrane on substrate, make amorphous silicon membrane fusion (Melting) afterwards after crystallization again (Re-crystallization) become polysilicon membrane.Figure 1A and Figure 1B are the generalized sections of the manufacturing process of existing low-temperature polysilicon film.General laser annealing processing procedure commonly used is quasi-molecule laser annealing (Excimer Laser Annealing abbreviates ELA an as) processing procedure.Please refer to Figure 1A, on substrate 100, form after the amorphous silicon membrane 102, carry out laser annealing (Laser Annealing) processing procedure by excimer pulsed laser beam 106 again, with amorphous silicon membrane 102 fusions, thereby the silicon molecule is recrystallized into into polysilicon membrane 102a, shown in Figure 1B.
Yet, because the crystallite dimension of the formed polysilicon membrane 102a of ELA processing procedure is too small, and dimensional homogeneity (uniformity) is not good, therefore have many grain boundaries (grain boundary) among the polysilicon membrane 102a, so that the only about 100～200cm of the mobility of electronics in the channel region of polysilicon membrane 102a
2/ Vsec, thereby the usefulness of thin-film transistor caused considerable influence.
For addressing the above problem, known proposition another kind is called the laser annealing processing procedure that continuously lateral solidifies (SequentialLateral Solidification abbreviates SLS as).Fig. 2 A to Fig. 2 B is depicted as the manufacturing process generalized section of existing another kind of low-temperature polysilicon film.
Please refer to Fig. 2 A, the SLS processing procedure utilizes light shield 104 to limit the scope that amorphous silicon membrane 102 is shone by laser beam 106, with the amorphous silicon membrane in the puddle zone 102, i.e. and the amorphous silicon membrane 102 of zone in 110.In some SLS processing procedure, light shield 104 is done translation motion by board control, so that laser beam sees through the hole 108 on the light shield 104 and shines all amorphous silicon membranes 102 in the zone 110.
Please refer to Fig. 2 B, after after a while, the amorphous silicon membrane 102 that is melted (amorphous silicon membrane 102 of zone in 110 just) will be nucleus and side direction is grown up with the amorphous silicon membrane 102 of not fusion, so in zone 110 formation polysilicon membrane 202a.
By Fig. 2 B as can be known, the SLS processing procedure can form the bigger polysilicon membrane 202a of crystallite dimension.In other words, less with the crystal grain boundary among the formed polysilicon membrane 202a of SLS processing procedure, therefore the SLS processing procedure is compared with traditional ELA processing procedure, the SLS processing procedure not only can improve the mobility of electronics in polysilicon membrane, and then the usefulness of raising thin-film transistor, can make that more the crystal orientation (grain orientation) of polysilicon membrane is more consistent.
Yet because the employed instrument and equipment of SLS processing procedure is comparatively expensive, and it is than the traditional E LA processing procedure use of Duoing special light shield together, so the cost of bulk crystal pipe on making is quite high.In addition, the SLS processing procedure still can't reduce and form polysilicon membrane required man-hour.
Summary of the invention
Therefore, the purpose of this utility model provides a kind of low-temperature polysilicon film transistor, and the crystal grain in its channel layer has preferable dimensional homogeneity, and crystal grain boundary is also less, makes this transistor have preferable element characteristic.
The utility model proposes a kind of low-temperature polysilicon film transistor, it is suitable for being configured on the substrate.This low-temperature polysilicon film transistor mainly is made of cap layer, polysilicon membrane and gate.Wherein cap layer is configured in substrate top, and has an interstitial area between itself and substrate.Polysilicon membrane is configured on the cap layer, and the source/drain regions that can divide into channel region and be positioned at the channel region both sides.Wherein channel region is positioned at the top of interstitial area, and the polysilicon membrane in the channel region is transistorized channel layer.Gate then is configured in the top of channel region.
Described according to embodiment of the present utility model, this low-temperature polysilicon film transistor also comprises the resilient coating that is configured on the substrate, it is unexpected that diffusion take place in order to stop the impurity in the substrate, and then influence the usefulness of element between cap layer and substrate in it in processing procedure.And in the present embodiment, interstitial area is for example between cap layer and resilient coating, and the coefficient of heat conduction that interstitial area had is lower than the coefficient of heat conduction of resilient coating and substrate.
Described according to embodiment of the present utility model, this low-temperature polysilicon film transistor also includes gate dielectric layer, and it is configured on the polysilicon membrane.
Described according to embodiment of the present utility model, the crystal grain of the polysilicon membrane in the channel region is for example greater than the crystal grain of the polysilicon membrane in the source/drain regions, thereby makes transistor have high drive current and lower leakage current.In addition, because the crystallite dimension in the channel region is bigger, therefore the quantity of crystal grain boundary wherein also is less than the quantity of the crystal grain boundary in the source/drain regions, is difficult for by the crystal grain boundary scattering, so have preferable electron mobility so electronics can be moved but by electric field in channel region.And the width of gate is preferably less than the size of the crystal grain in the channel region.In addition, in another embodiment, this gate for example is the double-gate electrode structure, more can reduce the influence that electronics directly is subjected to unique crystal grain boundary of passage central authorities, thereby obviously promotes transistorized usefulness.
Described according to embodiment of the present utility model, this low-temperature polysilicon film transistor also comprises dielectric layer, source/drain contact hole and source/drain conductor layer.Wherein, dielectric layer is disposed on the polysilicon membrane and covers gate.The source/drain contact hole all is configured in dielectric layer and the gate dielectric layer, and electrically contacts with source/drain regions.The source/drain conductor layer then is configured on the dielectric layer, and inserts the source/drain contact hole and be electrically connected with source/drain regions.
The crystal orientation of the crystal grain in the formed polysilicon membrane of the utility model all is parallel to the direction of the electric transmission under in working order of transistor backward, can thereby improve the mobility of electronics in channel region, and then improves transistorized task performance.
For above-mentioned and other purposes, feature and advantage of the present utility model can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. is described in detail as follows.
Description of drawings
Figure 1A and Figure 1B are the manufacturing process generalized sections of existing low-temperature polysilicon film.
Fig. 2 A to Fig. 2 B is depicted as the manufacturing process generalized section of existing another kind of low-temperature polysilicon film.
Figure 3 shows that the generalized section of the low-temperature polysilicon film transistor of a preferred embodiment of the present utility model.
Fig. 4 A is depicted as the top view of the low-temperature polysilicon film transistor among the embodiment of the present utility model.
Fig. 4 B is depicted as the top view of the low-temperature polysilicon film transistor among another embodiment of the present utility model.
Fig. 5 A to Fig. 5 E is depicted as the manufacturing process generalized section of channel layer of a kind of low-temperature polysilicon film transistor of the utility model one preferred embodiment.
Fig. 6 A to Fig. 6 D is corresponding diagram 5A to Fig. 5 E and its top view is shown respectively then.
Embodiment
The utility model is before changing amorphous silicon membrane the processing procedure of polysilicon membrane into, removing amorphous silicon membrane earlier desires to form the interstitial area low than the heat conductivity of both sides as the sacrifice layer below the zone of polysilicon passage in successive process, so that Shang Fang silicon crystal grain crystalline rate is slow than the crystalline rate of the silicon crystal grain in the two side areas herein, and then make crystal grain by both sides toward center side to growth, and in channel region, grow up to the crystal grain of large-size.Following examples so that those skilled in the art more understands the utility model, are not in order to limit the utility model in order to principle of the present utility model to be described.
Figure 3 shows that the generalized section of the low-temperature polysilicon film transistor of a preferred embodiment of the present utility model.Please refer to Fig. 3, low-temperature polysilicon film transistor 330 of the present utility model mainly is made of substrate 300, cap layer 306, polysilicon membrane 308a, gate 316 and 336 on source/drain conductor layer.Wherein, cap layer 306 is configured in the top of substrate 300, and in the present embodiment, for example disposes the resilient coating 302 between cap layer 306 and substrate 300 on the substrate 300, in order to stopping that unexpected diffusion takes place the impurity in the substrate in processing procedure, and then influence the usefulness of element.
Particularly, and between cap layer 306 and resilient coating 302 have more interstitial area 310.And for example has the low air of the coefficient of heat conduction or other gas in the interstitial area 310.
Polysilicon membrane 308a is configured on the cap layer 306, and the source/drain regions 318 that it can be divided into channel region 322 and be mixed with impurity (dopant), wherein channel region 322 is positioned at the top of interstitial area 310, and the polysilicon membrane 308a in the channel region 322 promptly is the polysilicon channel layer of low-temperature polysilicon film transistor 330.Gate 316 is configured in the top of the channel region 322 of polysilicon membrane 308a, and for example disposes gate dielectric layer 314 on the polysilicon membrane 308a.
What be worth paying special attention to is, in the present embodiment, silicon crystal grain 340 among the polysilicon membrane 308a in the channel region 322 is for example greater than the silicon crystal grain 350 among the polysilicon membrane 308a in the source/drain regions 318, and its preferred dimensions is slightly larger than half of length L of channel region 322 approximately, so low-temperature polysilicon film transistor 330 can have high drive current.And because crystal grain 340 sizes in the channel region 322 are bigger, so the quantity of the crystal grain boundary 360 in the channel region 322 can be less than the quantity of the crystal grain boundary 360 in the source/drain regions 318.And the crystal orientation of crystal grain is parallel to the transmission direction of electronics in low-temperature polysilicon film transistor 330, therefore when 330 in running order following times of low-temperature polysilicon film transistor, electron carrier can pass channel region 322 easily, and can not make electron mobility reduce because of the crystal grain boundary 360 too much scatterings in the channel region 322.
Particularly, the utility model can also be with gate 316 reduced width of low-temperature polysilicon film transistor 330, so that its size (shown in Fig. 4 A) less than crystal grain 340, can avoid the channel region of thin-film transistor to cross over crystal grain boundary, and then can make thin-film transistor can have preferable usefulness.Haveing the knack of this operator should be understood that in this so-called crystallite dimension and is often referred to crystal grain length on the direction that is parallel to gate width.
And except the width that dwindles gate, the utility model can also dispose double-gate electrode structure 416 on low-temperature polysilicon film transistor, and shown in Fig. 4 B, it shows the top view of the low-temperature polysilicon film transistor among another embodiment of the present utility model.This kind double-gate electrode structure 416 also can reduce the influence that electronics directly is subjected to unique crystal grain boundary of passage central authorities, thereby obviously promotes transistorized usefulness.
The utility model is finished the low-temperature polysilicon film transistor that above-mentioned channel region has preferable characteristic by special processing procedure, below will be illustrated the manufacture method of the channel layer of above-mentioned low-temperature polysilicon film transistor for embodiment.
Fig. 5 A to Fig. 5 E is depicted as the manufacturing process generalized section of channel layer of a kind of low-temperature polysilicon film transistor of the utility model one preferred embodiment.Fig. 6 A to Fig. 6 D is corresponding diagram 5A to Fig. 5 E and its top view is shown respectively then.
Please refer to Fig. 5 A, on substrate 300, form resilient coating (buffer layer) 302 and sacrifice layer 304 at first in regular turn, its formation method for example is chemical vapour deposition technique (Chemical VaporDeposition) or sputter (sputtering) method, and the material of sacrifice layer 304 for example is a metal material.It should be noted that resilient coating 302 is element optionally, its function embodiment as described above is described, repeats no more herein.Can be whether and have the knack of this operator according to the required existence that decides resilient coating 302 of actual processing procedure, the utility model is not limited it.And sacrifice layer 304 for example is one to be configured in the rete of the rectangle pattern on the resilient coating 302, as shown in Figure 6A.
Please refer to Fig. 5 B and Fig. 6 B, on resilient coating 302, form cap layer 306 and amorphous silicon membrane 308 in regular turn, and cover sacrifice layer 304.Wherein, will be forming the channel layer of low-temperature polysilicon film transistor in the zone above the sacrifice layer 304 312 in successive process, and in the both sides in zone 312, form source/drain regions.Therefore, the width of sacrifice layer 304 promptly determines the length of the channel layer of this low-temperature polysilicon film transistor.In other words, can effectively control the length of channel region in the low-temperature polysilicon film transistor by the width of control sacrifice layer 304.
Please refer to Fig. 5 C and Fig. 6 C, then remove sacrifice layer 304,, and for example have air in the interstitial area 310 with formation interstitial area 310 between cap layer 306 and resilient coating 302.The practice of this step for example is to remove sacrifice layer 304 with Wet-type etching, just the structure that Fig. 5 B is illustrated is soaked in (not shown) among the etching solution, and this etching solution to the etch-rate of sacrifice layer 304 much larger than its etch-rate, so this step can remove sacrifice layer 304 under the situation that other retes all are kept perfectly to other retes.
Please be simultaneously with reference to Fig. 5 D and Fig. 5 E, after forming interstitial area 310, then carry out the laser annealing processing procedure so that crystallization and form polysilicon membrane 308a again after amorphous silicon membrane 308 fusions, and in forming polysilicon channel layer 522 (just being positioned at the polysilicon membrane 308a within the zone 312) on the cap layer 306 of interstitial area 310 tops.And the employed laser annealing processing procedure of present embodiment for example is the quasi-molecule laser annealing processing procedure, and shown in Fig. 5 D, it is to utilize excimer pulsed laser beam 326 irradiation amorphous silicon membranes 308 so that its melting and become the liquid-state silicon (not shown).After after a while, liquid-state silicon can slowly be lowered the temperature and is recrystallised to polysilicon membrane.At this moment, because zone 312 is positioned at the top of interstitial area 310, and for example has air in the interstitial area 310, and the coefficient of heat conduction of air is about 0.025W/cmK, much smaller than the coefficient of heat conduction of cap layer 306 and resilient coating 302.Therefore, the crystalline rate of the liquid-state silicon of zone in 312 can be slow than the crystalline rate of the liquid-state silicon of both sides.In other words, in solidification process, silicon atom will 312 central authorities laterally become germination and form polysilicon membrane 308a toward the zone by both sides, and the polysilicon membrane 308a in the zone 312 is transistorized polysilicon channel layer 522, shown in Fig. 5 E and Fig. 6 D.
Particularly, because the crystal grain-growth in the zone 312 is slower, therefore formed crystallite dimension is also just big than formed crystal grain in the two side areas, that is to say that the crystal grain in the polysilicon channel layer 522 has bigger size, and it for example is slightly larger than polysilicon channel layer 322 length L half.
In addition, because the quantity of the crystal grain boundary in the polysilicon channel layer 322 is less than the quantity of crystal grain boundary in the two side areas, so electronics can have preferable mobility in polysilicon channel layer 322, and then improves transistorized task performance.
In sum, low-temperature polysilicon film transistor of the present utility model has following advantage:
1. because the crystal grain in this transistorized channel region has bigger size and preferable dimensional homogeneity, therefore transistor of the present utility model has high drive current and high electron mobility.
2. utilize the formed polysilicon membrane of processing procedure of the present utility model, wherein the crystal orientation of crystal grain all is parallel to the transmission direction of electronics in transistor, so the utility model can improve the mobility of electronics in channel region, and then improves transistorized task performance.
3. the width of the channel region in this transistor and the length width and the length that depend on sacrifice layer.Therefore, the breadth length ratio of channel region can be complied with the required size of adjusting sacrifice layer of actual processing procedure, and processing procedure nargin is bigger.
4. manufacturing equipment of the present utility model is compatible with existing manufacturing equipment, it for example can reach continuously lateral curing (Sequential LateralSolidification by the equipment of existing quasi-molecule laser annealing processing procedure, SLS) level of processing procedure, that is to say, the utility model is when improving product quality, also can save the process apparatus cost, to reach maximum productive profit.
Though the utility model discloses as above with preferred embodiment; yet it is not in order to limit the utility model; anyly have the knack of this operator; in not breaking away from spirit and scope of the present utility model; when doing a little change and retouching, therefore protection range of the present utility model is as the criterion with accompanying claims.
Description of reference numerals
100,300: substrate
102,308: amorphous silicon membrane
102a, 202a, 308a: polysilicon membrane
104: light shield
106,326: excimer pulsed laser beam
108: hole
110,312: the zone
302: resilient coating
304: sacrifice layer
306: cap layer
310: interstitial area
314: gate dielectric layer
316: gate
318: source/drain regions
322: channel region
324: dielectric layer
330: low-temperature polysilicon film transistor
332: the source/drain contact hole
336: the source/drain conductor layer
340,350: silicon crystal grain
416: the double-gate electrode structure
522: polysilicon channel layer
Claims (9)
1. low-temperature polysilicon film transistor, it is suitable for being configured on the substrate, it is characterized in that, and this low-temperature polysilicon film transistor comprises:
One cap layer, it is disposed at this substrate top, wherein has an interstitial area between this cap layer and this substrate;
One polysilicon membrane, it is disposed on this cap layer, and this polysilicon membrane comprises that a channel region and is positioned at the source/drain regions of these channel region both sides, and wherein this channel region is positioned at this interstitial area top; And
One gate, it is disposed at this channel region top of this polysilicon membrane.
2. low-temperature polysilicon film transistor as claimed in claim 1 is characterized in that, also comprises a resilient coating, and it is disposed between this substrate and this cap layer, and this interstitial area is between this cap layer and this resilient coating.
3. low-temperature polysilicon film transistor as claimed in claim 2 is characterized in that the coefficient of heat conduction that this interstitial area had is lower than the coefficient of heat conduction of this resilient coating.
4. low-temperature polysilicon film transistor as claimed in claim 1 is characterized in that the coefficient of heat conduction that this interstitial area had is lower than the coefficient of heat conduction of this substrate.
5. low-temperature polysilicon film transistor as claimed in claim 1 is characterized in that, also comprises a gate dielectric layer, and it is disposed on this polysilicon membrane.
6. low-temperature polysilicon film transistor as claimed in claim 1 is characterized in that, the crystallite dimension in this channel region of this polysilicon membrane is greater than the crystallite dimension in this source/drain regions of this polysilicon membrane.
7. low-temperature polysilicon film transistor as claimed in claim 1 is characterized in that this gate width is less than the crystallite dimension in this channel region.
8. low-temperature polysilicon film transistor as claimed in claim 1 is characterized in that, this gate is a pair of gate structure.
9. low-temperature polysilicon film transistor as claimed in claim 1 is characterized in that, also comprises:
One dielectric layer, it is disposed on this polysilicon membrane and this gate, and wherein this dielectric layer has a plurality of contact holes, to expose this source/drain regions of this polysilicon membrane; And
The source conductor layer, it is disposed on this dielectric layer, and this source/drain conductor layer is electrically connected with this source/drain regions of this polysilicon membrane by these contact holes in this dielectric layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420073977 CN2717022Y (en) | 2004-07-16 | 2004-07-16 | Low-temperature polysilicon thin-film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200420073977 CN2717022Y (en) | 2004-07-16 | 2004-07-16 | Low-temperature polysilicon thin-film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2717022Y true CN2717022Y (en) | 2005-08-10 |
Family
ID=34874285
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200420073977 Expired - Fee Related CN2717022Y (en) | 2004-07-16 | 2004-07-16 | Low-temperature polysilicon thin-film transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2717022Y (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100391009C (en) * | 2004-07-16 | 2008-05-28 | 友达光电股份有限公司 | Low-temperature polysilicon thin film transistor and method for manufacturing its channel layer |
| CN103887244A (en) * | 2014-03-07 | 2014-06-25 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method and display device |
-
2004
- 2004-07-16 CN CN 200420073977 patent/CN2717022Y/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100391009C (en) * | 2004-07-16 | 2008-05-28 | 友达光电股份有限公司 | Low-temperature polysilicon thin film transistor and method for manufacturing its channel layer |
| CN103887244A (en) * | 2014-03-07 | 2014-06-25 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method and display device |
| US9773813B2 (en) | 2014-03-07 | 2017-09-26 | Boe Technology Group Co., Ltd. | Thin film transistor and a manufacturing method thereof, array substrate and a manufacturing method thereof, display device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1050221C (en) | Method for forming polycrystalline thin-film and method for fabricating thin-film transistor | |
| CN1187791C (en) | Method for crystallizing silicon layer | |
| CN2751447Y (en) | Multi-grid transistor | |
| CN1691340A (en) | Electronic device and method of manufacturing the same | |
| CN1310284C (en) | Crystallization method of amorphous silicon for thin film transistor | |
| CN1457103A (en) | Thin film transistor and manufacturing method thereof | |
| JP3522441B2 (en) | Semiconductor device | |
| CN1051640C (en) | Semiconductor device and method for fabricating the same | |
| US20060008953A1 (en) | Structure of ltps-tft and method of fabricating channel layer thereof | |
| CN1770472A (en) | Method of forming a polysilicon film, thin film transistor including a polysilicon film and method of manufacturing the same | |
| US6025217A (en) | Method of forming polycrystalline semiconductor thin film | |
| CN1716529A (en) | Crystallization method and apparatus thereof | |
| CN1638022A (en) | Method for forming polycrystalline silicon film | |
| JP2004039765A (en) | Thin film semiconductor device, its manufacture and image display device | |
| CN2717022Y (en) | Low-temperature polysilicon thin-film transistor | |
| JP5232360B2 (en) | Semiconductor device and manufacturing method thereof | |
| CN1722467A (en) | Low-temperature polysilicon thin film transistor and method for manufacturing its channel layer | |
| CN1315156C (en) | Multicrystalline silicon film manufacturing method | |
| US20040224446A1 (en) | [structure of thin-film transistor and method and equipment for fabricating the structure] | |
| CN1581427A (en) | Multicrystalline silicon film manufacturing method | |
| JP4987198B2 (en) | Method for manufacturing polycrystalline silicon thin film transistor | |
| CN1217405C (en) | Semiconductor device and its mfg. method, electrooptical device and electronic machine | |
| US20050136612A1 (en) | Method of forming poly-silicon crystallization | |
| CN2717021Y (en) | Low-temperature polysilicon thin-film transistor | |
| JPH11284198A (en) | Semiconductor device and its manufacture |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: YOUDA PHOTOELECTRIC CO., LTD. Free format text: FORMER NAME OR ADDRESS: GUANGHUI ELECTRONIC CO., LTD. |
|
| CP03 | Change of name, title or address |
Address after: Postcode of Taiwan, Hsinchu, china: Patentee after: AU Optronics Corporation Address before: Taoyuan County, Taiwan province: Patentee before: Guanghui Electronic Co., Ltd. |
|
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |