JP4247167B2 - パッケージの構造 - Google Patents
パッケージの構造 Download PDFInfo
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- JP4247167B2 JP4247167B2 JP2004234967A JP2004234967A JP4247167B2 JP 4247167 B2 JP4247167 B2 JP 4247167B2 JP 2004234967 A JP2004234967 A JP 2004234967A JP 2004234967 A JP2004234967 A JP 2004234967A JP 4247167 B2 JP4247167 B2 JP 4247167B2
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- Prior art keywords
- insulating layer
- alloy
- layer
- conductive layer
- patterned
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- 239000010410 layer Substances 0.000 claims description 97
- 239000000463 material Substances 0.000 claims description 21
- 229910000679 solder Inorganic materials 0.000 claims description 19
- 239000011241 protective layer Substances 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000004642 Polyimide Substances 0.000 claims description 13
- 229920001721 polyimide Polymers 0.000 claims description 13
- 239000004593 Epoxy Substances 0.000 claims description 9
- 239000010949 copper Substances 0.000 claims description 9
- KPUWHANPEXNPJT-UHFFFAOYSA-N disiloxane Chemical class [SiH3]O[SiH3] KPUWHANPEXNPJT-UHFFFAOYSA-N 0.000 claims description 8
- 229920000642 polymer Polymers 0.000 claims description 8
- 229920005989 resin Polymers 0.000 claims description 8
- 239000011347 resin Substances 0.000 claims description 8
- 229910001020 Au alloy Inorganic materials 0.000 claims description 7
- 229910000990 Ni alloy Inorganic materials 0.000 claims description 7
- 229910045601 alloy Inorganic materials 0.000 claims description 7
- 239000000956 alloy Substances 0.000 claims description 7
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 6
- 229910001069 Ti alloy Inorganic materials 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 230000035882 stress Effects 0.000 description 8
- 238000012536 packaging technology Methods 0.000 description 4
- 238000005728 strengthening Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 230000008646 thermal stress Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000005336 cracking Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000002277 temperature effect Effects 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
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Description
201 金属パッド
202 保護層
203 絶縁層
204 再分配層(RDL)
205 絶縁層
206 はんだボール
208 絶縁層
Claims (5)
- 保護層上に、その上に形成される導電層が積層方向に振幅を有するジグザグ形となるよう、選択的に形成されたパターン化された第1の絶縁層と、
前記第1の絶縁層及び前記保護層上に形成され、前記第1の絶縁層の有無によって、前記保護層及び前記第1の絶縁層の積層方向に振幅を有するジグザグ形に形成された前記導電層と、
前記導電層上に形成され、複数の開口部を有する第2の絶縁層であって、各開口部が、外部部品と電気的に接続する接触金属ボールを有する第2の絶縁層と、
を含むパッケージの構造であって、
前記導電層は、前記第1の絶縁層の間の複数の空間に形成される、
ことを特徴とするパッケージの構造。 - 前記パッケージの構造の固定された領域における前記導電層は、前記接触金属ボールが印刷回路基板上に設置されるときに金属パッドを直接引き伸ばさず、前記ジグザグ形の導電層が応力を吸収すべく前記パッケージの緩衝部材として作用する、請求項1に記載の構造。
- 前記パターン化された第1の絶縁層と前記導電層との間に形成されたパターン化された第3の絶縁層をさらに含み、前記第3の絶縁層の材料が、BCB、シロキサンポリマー(SINR)、エポキシ、ポリイミド又は樹脂を含み、前記第1の絶縁層の材料が、BCB、シロキサンポリマー(SINR)、エポキシ、ポリイミド又は樹脂を含み、前記保護層の材料が、ポリイミドであり、前記導電層の材料が、合金であり、前記合金が、Ti/Cu合金又はCu/Ni/Au合金であり、前記Ti/Cu合金がスパッタリングにより形成され、前記Cu/Ni/Au合金が電気メッキにより形成され、前記合金の厚さはおよそ10乃至20ミクロンであり、前記金属パッドの材料が、アルミニウム又は銅であり、前記第2の絶縁層の材料が、BCB、シロキサンポリマー(SINR)、エポキシ、ポリイミド又は樹脂を含み、前記接触金属ボールがはんだボールである、請求項1に記載の構造。
- 下側層上に、その上に形成される導電層が積層方向に振幅を有するジグザグ形となるよう、選択的に形成されたパターン化された絶縁層と、
前記パターン化された絶縁層の有無によって、応力を吸収すべく前記下側層及び前記パターン化された絶縁層の積層方向に振幅を有するジグザグ形となるように前記パターン化された絶縁層及び下側層上に構成された前記導電層と、
を含むパッケージの構造であって、
前記導電層は、前記パターン化された絶縁層の間の複数の空間に形成される、
ことを特徴とするパッケージの構造。 - 前記絶縁層の材料が、BCB、シロキサンポリマー(SINR)、エポキシ、ポリイミド、又は樹脂を含み、前記導電層の材料が合金であり、前記合金がTi/Cu合金又はCu/Ni/Au合金を含み、前記Ti/Cu合金がスパッタリングによって形成され、前記Cu/Ni/Au合金が電気メッキによって形成され、前記合金の厚さがおよそ10乃至20ミクロンである、請求項4に記載の構造。
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JP (1) | JP4247167B2 (ja) |
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CN (1) | CN100447994C (ja) |
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Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI254428B (en) * | 2004-11-24 | 2006-05-01 | Advanced Chip Eng Tech Inc | FCBGA package structure |
KR100764055B1 (ko) * | 2006-09-07 | 2007-10-08 | 삼성전자주식회사 | 웨이퍼 레벨 칩 스케일 패키지 및 칩 스케일 패키지의 제조방법 |
US20080088004A1 (en) * | 2006-10-17 | 2008-04-17 | Advanced Chip Engineering Technology Inc. | Wafer level package structure with build up layers |
US20080116564A1 (en) * | 2006-11-21 | 2008-05-22 | Advanced Chip Engineering Technology Inc. | Wafer level package with die receiving cavity and method of the same |
KR100858242B1 (ko) * | 2007-04-04 | 2008-09-12 | 삼성전자주식회사 | 재배선 구조를 포함하는 반도체 소자 및 그 형성 방법 |
TWI353644B (en) * | 2007-04-25 | 2011-12-01 | Ind Tech Res Inst | Wafer level packaging structure |
US9059083B2 (en) | 2007-09-14 | 2015-06-16 | Infineon Technologies Ag | Semiconductor device |
CN101882589B (zh) * | 2009-05-06 | 2013-01-16 | 台湾积体电路制造股份有限公司 | 集成电路结构的形成方法 |
US8258633B2 (en) * | 2010-03-31 | 2012-09-04 | Infineon Technologies Ag | Semiconductor package and multichip arrangement having a polymer layer and an encapsulant |
CN103247546B (zh) * | 2013-04-17 | 2016-03-30 | 南通富士通微电子股份有限公司 | 半导体器件芯片级封装方法 |
CN103258805B (zh) * | 2013-04-17 | 2015-11-25 | 南通富士通微电子股份有限公司 | 半导体器件芯片级封装结构 |
US10026707B2 (en) * | 2016-09-23 | 2018-07-17 | Microchip Technology Incorportated | Wafer level package and method |
US20190259731A1 (en) * | 2016-11-09 | 2019-08-22 | Unisem (M) Berhad | Substrate based fan-out wafer level packaging |
CN111211104B (zh) * | 2018-11-22 | 2021-09-07 | 华邦电子股份有限公司 | 线路结构及其制造方法 |
TWI789748B (zh) * | 2021-04-26 | 2023-01-11 | 友達光電股份有限公司 | 電子裝置及其製造方法 |
Family Cites Families (38)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS601846A (ja) * | 1983-06-18 | 1985-01-08 | Toshiba Corp | 多層配線構造の半導体装置とその製造方法 |
JPH04196552A (ja) * | 1990-11-28 | 1992-07-16 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JPH05251573A (ja) * | 1992-03-04 | 1993-09-28 | Nec Yamagata Ltd | 半導体装置 |
JP3057130B2 (ja) * | 1993-02-18 | 2000-06-26 | 三菱電機株式会社 | 樹脂封止型半導体パッケージおよびその製造方法 |
US5391397A (en) * | 1994-04-05 | 1995-02-21 | Motorola, Inc. | Method of adhesion to a polyimide surface by formation of covalent bonds |
JP2773660B2 (ja) * | 1994-10-27 | 1998-07-09 | 日本電気株式会社 | 半導体装置 |
GB9514777D0 (en) * | 1995-07-19 | 1995-09-20 | Osprey Metals Ltd | Silicon alloys for electronic packaging |
SG45122A1 (en) * | 1995-10-28 | 1998-01-16 | Inst Of Microelectronics | Low cost and highly reliable chip-sized package |
US6284563B1 (en) * | 1995-10-31 | 2001-09-04 | Tessera, Inc. | Method of making compliant microelectronic assemblies |
JP3437369B2 (ja) * | 1996-03-19 | 2003-08-18 | 松下電器産業株式会社 | チップキャリアおよびこれを用いた半導体装置 |
JPH09330934A (ja) * | 1996-06-12 | 1997-12-22 | Toshiba Corp | 半導体装置及びその製造方法 |
TW571373B (en) * | 1996-12-04 | 2004-01-11 | Seiko Epson Corp | Semiconductor device, circuit substrate, and electronic machine |
JP3068534B2 (ja) * | 1997-10-14 | 2000-07-24 | 九州日本電気株式会社 | 半導体装置 |
KR20000002962A (ko) * | 1998-06-24 | 2000-01-15 | 윤종용 | 웨이퍼레벨의 칩스케일 패키지 및 그 제조방법 |
US6103552A (en) * | 1998-08-10 | 2000-08-15 | Lin; Mou-Shiung | Wafer scale packaging scheme |
KR100269540B1 (ko) * | 1998-08-28 | 2000-10-16 | 윤종용 | 웨이퍼 상태에서의 칩 스케일 패키지 제조 방법 |
JP2000294730A (ja) * | 1999-04-09 | 2000-10-20 | Mitsubishi Electric Corp | システムlsiチップ及びその製造方法 |
JP3651597B2 (ja) * | 1999-06-15 | 2005-05-25 | 株式会社フジクラ | 半導体パッケージ、半導体装置、電子装置及び半導体パッケージの製造方法 |
JP2001024085A (ja) * | 1999-07-12 | 2001-01-26 | Nec Corp | 半導体装置 |
US6277669B1 (en) * | 1999-09-15 | 2001-08-21 | Industrial Technology Research Institute | Wafer level packaging method and packages formed |
US6528349B1 (en) * | 1999-10-26 | 2003-03-04 | Georgia Tech Research Corporation | Monolithically-fabricated compliant wafer-level package with wafer level reliability and functionality testability |
TW478089B (en) * | 1999-10-29 | 2002-03-01 | Hitachi Ltd | Semiconductor device and the manufacturing method thereof |
KR100338949B1 (ko) * | 1999-12-14 | 2002-05-31 | 박종섭 | 반도체 패키지의 배선 구조 |
KR100361084B1 (ko) * | 2000-01-21 | 2002-11-18 | 주식회사 하이닉스반도체 | 반도체 패키지 및 그 제조방법 |
JP4177950B2 (ja) * | 2000-03-28 | 2008-11-05 | ローム株式会社 | 半導体装置の製造方法 |
DE10016132A1 (de) * | 2000-03-31 | 2001-10-18 | Infineon Technologies Ag | Elektronisches Bauelement mit flexiblen Kontaktierungsstellen und Verfahren zu dessen Herstellung |
US6521970B1 (en) * | 2000-09-01 | 2003-02-18 | National Semiconductor Corporation | Chip scale package with compliant leads |
JP2002198374A (ja) * | 2000-10-16 | 2002-07-12 | Sharp Corp | 半導体装置およびその製造方法 |
US6433427B1 (en) * | 2001-01-16 | 2002-08-13 | Industrial Technology Research Institute | Wafer level package incorporating dual stress buffer layers for I/O redistribution and method for fabrication |
JP2003017522A (ja) * | 2001-06-28 | 2003-01-17 | Sanyo Electric Co Ltd | 半導体装置とその製造方法 |
JP4068838B2 (ja) * | 2001-12-07 | 2008-03-26 | 株式会社日立製作所 | 半導体装置の製造方法 |
US6720212B2 (en) * | 2002-03-14 | 2004-04-13 | Infineon Technologies Ag | Method of eliminating back-end rerouting in ball grid array packaging |
US6756671B2 (en) * | 2002-07-05 | 2004-06-29 | Taiwan Semiconductor Manufacturing Co., Ltd | Microelectronic device with a redistribution layer having a step shaped portion and method of making the same |
US6656827B1 (en) * | 2002-10-17 | 2003-12-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Electrical performance enhanced wafer level chip scale package with ground |
US6806570B1 (en) * | 2002-10-24 | 2004-10-19 | Megic Corporation | Thermal compliant semiconductor chip wiring structure for chip scale packaging |
JP3611561B2 (ja) * | 2002-11-18 | 2005-01-19 | 沖電気工業株式会社 | 半導体装置 |
JP2004214561A (ja) * | 2003-01-08 | 2004-07-29 | Oki Electric Ind Co Ltd | 半導体装置及びその製造方法 |
TWI222687B (en) * | 2003-08-14 | 2004-10-21 | Advanced Semiconductor Eng | Semiconductor chip with bumps and method for manufacturing the same |
-
2004
- 2004-04-30 US US10/835,571 patent/US7259468B2/en not_active Expired - Lifetime
- 2004-05-24 TW TW093114663A patent/TWI242278B/zh not_active IP Right Cessation
- 2004-05-31 CN CNB2004100464290A patent/CN100447994C/zh not_active Expired - Fee Related
- 2004-06-09 SG SG200403407A patent/SG128464A1/en unknown
- 2004-06-30 KR KR1020040050090A patent/KR100710977B1/ko not_active IP Right Cessation
- 2004-07-12 DE DE102004033647A patent/DE102004033647B4/de not_active Expired - Fee Related
- 2004-08-12 JP JP2004234967A patent/JP4247167B2/ja not_active Expired - Fee Related
- 2004-11-24 US US10/997,343 patent/US20050242427A1/en not_active Abandoned
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SG128464A1 (en) | 2007-01-30 |
DE102004033647B4 (de) | 2008-05-15 |
TW200536087A (en) | 2005-11-01 |
US20050242427A1 (en) | 2005-11-03 |
CN100447994C (zh) | 2008-12-31 |
CN1694247A (zh) | 2005-11-09 |
US20050242418A1 (en) | 2005-11-03 |
KR100710977B1 (ko) | 2007-04-24 |
KR20050105085A (ko) | 2005-11-03 |
DE102004033647A1 (de) | 2005-11-17 |
US7259468B2 (en) | 2007-08-21 |
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TWI242278B (en) | 2005-10-21 |
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