JP4213478B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP4213478B2
JP4213478B2 JP2003005766A JP2003005766A JP4213478B2 JP 4213478 B2 JP4213478 B2 JP 4213478B2 JP 2003005766 A JP2003005766 A JP 2003005766A JP 2003005766 A JP2003005766 A JP 2003005766A JP 4213478 B2 JP4213478 B2 JP 4213478B2
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JP
Japan
Prior art keywords
electrode
support
semiconductor device
manufacturing
organic film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2003005766A
Other languages
English (en)
Japanese (ja)
Other versions
JP2004221240A (ja
JP2004221240A5 (enExample
Inventor
義彦 根本
知徳 藤井
昌宏 春原
知稔 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Shinko Electric Industries Co Ltd
Sharp Corp
Taiyo Yuden Co Ltd
Original Assignee
Renesas Technology Corp
Shinko Electric Industries Co Ltd
Sharp Corp
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp, Shinko Electric Industries Co Ltd, Sharp Corp, Taiyo Yuden Co Ltd filed Critical Renesas Technology Corp
Priority to JP2003005766A priority Critical patent/JP4213478B2/ja
Priority to US10/629,695 priority patent/US6875672B2/en
Priority to TW092120782A priority patent/TWI247393B/zh
Priority to KR1020030061407A priority patent/KR100586865B1/ko
Priority to DE10346581A priority patent/DE10346581B4/de
Publication of JP2004221240A publication Critical patent/JP2004221240A/ja
Publication of JP2004221240A5 publication Critical patent/JP2004221240A5/ja
Application granted granted Critical
Publication of JP4213478B2 publication Critical patent/JP4213478B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354—Coating
    • H01L2224/13599—Material
    • H01L2224/136—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/8121—Applying energy for connecting using a reflow oven
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12044—OLED
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/928—Front and rear surface processing

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2003005766A 2003-01-14 2003-01-14 半導体装置の製造方法 Expired - Fee Related JP4213478B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2003005766A JP4213478B2 (ja) 2003-01-14 2003-01-14 半導体装置の製造方法
US10/629,695 US6875672B2 (en) 2003-01-14 2003-07-30 Method of manufacturing a semiconductor device with penetration electrodes that protrude from a rear side of a substrate formed by thinning the substrate
TW092120782A TWI247393B (en) 2003-01-14 2003-07-30 Method of manufacturing semiconductor device
KR1020030061407A KR100586865B1 (ko) 2003-01-14 2003-09-03 반도체장치의 제조방법
DE10346581A DE10346581B4 (de) 2003-01-14 2003-10-07 Verfahren zum Herstellen einer Halbleitervorrichtung

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003005766A JP4213478B2 (ja) 2003-01-14 2003-01-14 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2004221240A JP2004221240A (ja) 2004-08-05
JP2004221240A5 JP2004221240A5 (enExample) 2006-03-02
JP4213478B2 true JP4213478B2 (ja) 2009-01-21

Family

ID=32588500

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003005766A Expired - Fee Related JP4213478B2 (ja) 2003-01-14 2003-01-14 半導体装置の製造方法

Country Status (5)

Country Link
US (1) US6875672B2 (enExample)
JP (1) JP4213478B2 (enExample)
KR (1) KR100586865B1 (enExample)
DE (1) DE10346581B4 (enExample)
TW (1) TWI247393B (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6809421B1 (en) 1996-12-02 2004-10-26 Kabushiki Kaisha Toshiba Multichip semiconductor device, chip therefor and method of formation thereof
JP4072677B2 (ja) * 2003-01-15 2008-04-09 セイコーエプソン株式会社 半導体チップ、半導体ウエハ、半導体装置及びその製造方法、回路基板並びに電子機器
JP4528100B2 (ja) * 2004-11-25 2010-08-18 新光電気工業株式会社 半導体装置及びその製造方法
JP4698296B2 (ja) * 2005-06-17 2011-06-08 新光電気工業株式会社 貫通電極を有する半導体装置の製造方法
JP5193503B2 (ja) 2007-06-04 2013-05-08 新光電気工業株式会社 貫通電極付き基板及びその製造方法
JP4784641B2 (ja) 2008-12-23 2011-10-05 株式会社デンソー 半導体装置およびその製造方法
US20100171197A1 (en) * 2009-01-05 2010-07-08 Hung-Pin Chang Isolation Structure for Stacked Dies
US9177893B2 (en) 2011-05-17 2015-11-03 Infineon Technologies Ag Semiconductor component with a front side and a back side metallization layer and manufacturing method thereof
US8900994B2 (en) 2011-06-09 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method for producing a protective structure
US8558389B2 (en) 2011-12-08 2013-10-15 Stats Chippac, Ltd. Semiconductor device and method of forming guard ring around conductive TSV through semiconductor wafer
DE102013103723B4 (de) * 2013-04-12 2023-02-02 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Verfahren zur Herstellung eines Bauteils
JP6557953B2 (ja) * 2014-09-09 2019-08-14 大日本印刷株式会社 構造体及びその製造方法
JP7150632B2 (ja) * 2019-02-13 2022-10-11 キオクシア株式会社 半導体装置の製造方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6474891A (en) * 1987-09-17 1989-03-20 Toshiba Corp Telephone exchange
US4978639A (en) * 1989-01-10 1990-12-18 Avantek, Inc. Method for the simultaneous formation of via-holes and wraparound plating on semiconductor chips
JP2839376B2 (ja) * 1991-02-05 1998-12-16 三菱電機株式会社 半導体装置の製造方法
US5447871A (en) * 1993-03-05 1995-09-05 Goldstein; Edward F. Electrically conductive interconnection through a body of semiconductor material
US5424245A (en) * 1994-01-04 1995-06-13 Motorola, Inc. Method of forming vias through two-sided substrate
US5646067A (en) * 1995-06-05 1997-07-08 Harris Corporation Method of bonding wafers having vias including conductive material
DE19543540C1 (de) * 1995-11-22 1996-11-21 Siemens Ag Vertikal integriertes Halbleiterbauelement mit zwei miteinander verbundenen Substraten und Herstellungsverfahren dafür
EP2270846A3 (en) * 1996-10-29 2011-12-21 ALLVIA, Inc. Integrated circuits and methods for their fabrication
JPH1074891A (ja) 1997-08-07 1998-03-17 Nec Corp 半導体装置
JP3184493B2 (ja) * 1997-10-01 2001-07-09 松下電子工業株式会社 電子装置の製造方法
EP0926726A1 (en) * 1997-12-16 1999-06-30 STMicroelectronics S.r.l. Fabrication process and electronic device having front-back through contacts for bonding onto boards
JP2001026326A (ja) 1999-07-14 2001-01-30 Ricoh Co Ltd 給紙分離装置
JP2001102523A (ja) * 1999-09-28 2001-04-13 Sony Corp 薄膜デバイスおよびその製造方法
US6322903B1 (en) * 1999-12-06 2001-11-27 Tru-Si Technologies, Inc. Package of integrated circuits and vertical integration
EP1351288B1 (en) * 2002-04-05 2015-10-28 STMicroelectronics Srl Process for manufacturing an insulated interconnection through a body of semiconductor material and corresponding semiconductor device
JP4035066B2 (ja) * 2003-02-04 2008-01-16 株式会社ルネサステクノロジ 半導体装置の製造方法

Also Published As

Publication number Publication date
KR100586865B1 (ko) 2006-06-07
DE10346581A1 (de) 2004-07-22
US20040137705A1 (en) 2004-07-15
JP2004221240A (ja) 2004-08-05
US6875672B2 (en) 2005-04-05
KR20040065142A (ko) 2004-07-21
TWI247393B (en) 2006-01-11
DE10346581B4 (de) 2007-12-27
TW200412657A (en) 2004-07-16

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