JP4184586B2 - 半導体記憶装置 - Google Patents

半導体記憶装置 Download PDF

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Publication number
JP4184586B2
JP4184586B2 JP2000297443A JP2000297443A JP4184586B2 JP 4184586 B2 JP4184586 B2 JP 4184586B2 JP 2000297443 A JP2000297443 A JP 2000297443A JP 2000297443 A JP2000297443 A JP 2000297443A JP 4184586 B2 JP4184586 B2 JP 4184586B2
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JP
Japan
Prior art keywords
data
circuit
memory cell
page
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2000297443A
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English (en)
Japanese (ja)
Other versions
JP2002109893A5 (enrdf_load_stackoverflow
JP2002109893A (ja
Inventor
昇 柴田
智晴 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2000297443A priority Critical patent/JP4184586B2/ja
Priority to TW090122891A priority patent/TW543200B/zh
Priority to CNB2004100421793A priority patent/CN100431045C/zh
Priority to CN2007101802300A priority patent/CN101154459B/zh
Priority to KR10-2001-0058271A priority patent/KR100458411B1/ko
Priority to CN200710180232XA priority patent/CN101154465B/zh
Priority to CNB011372443A priority patent/CN1178228C/zh
Priority to CN2007101802315A priority patent/CN101154461B/zh
Priority to US09/957,019 priority patent/US6600676B2/en
Publication of JP2002109893A publication Critical patent/JP2002109893A/ja
Priority to US10/442,995 priority patent/US6937512B2/en
Priority to US11/194,716 priority patent/US7106627B2/en
Publication of JP2002109893A5 publication Critical patent/JP2002109893A5/ja
Priority to US11/530,340 priority patent/US7295469B2/en
Priority to US11/772,271 priority patent/US7613046B2/en
Application granted granted Critical
Publication of JP4184586B2 publication Critical patent/JP4184586B2/ja
Priority to US12/576,638 priority patent/US7894259B2/en
Priority to US13/012,030 priority patent/US8189389B2/en
Priority to US13/471,143 priority patent/US8885408B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628Programming or writing circuits; Data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/08Address circuits; Decoders; Word-line control circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/22Safety or protection circuits preventing unauthorised or accidental access to memory cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436Arrangements for verifying correct programming or erasure
    • G11C16/3454Arrangements for verifying correct programming or for detecting overprogrammed cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/78Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/83Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption
    • G11C29/832Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption with disconnection of faulty elements
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436Arrangements for verifying correct programming or erasure
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2211/00Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562Multilevel memory programming aspects
    • G11C2211/5621Multilevel programming verification
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2211/00Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564Miscellaneous aspects
    • G11C2211/5641Multilevel memory having cells with different number of storage levels
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
JP2000297443A 2000-09-28 2000-09-28 半導体記憶装置 Expired - Lifetime JP4184586B2 (ja)

Priority Applications (16)

Application Number Priority Date Filing Date Title
JP2000297443A JP4184586B2 (ja) 2000-09-28 2000-09-28 半導体記憶装置
TW090122891A TW543200B (en) 2000-09-28 2001-09-14 Nonvolatile semiconductor memory device
CN2007101802300A CN101154459B (zh) 2000-09-28 2001-09-20 半导体存储装置
KR10-2001-0058271A KR100458411B1 (ko) 2000-09-28 2001-09-20 불휘발성 반도체 기억 장치
CN200710180232XA CN101154465B (zh) 2000-09-28 2001-09-20 半导体存储装置
CNB011372443A CN1178228C (zh) 2000-09-28 2001-09-20 非易失半导体存储装置
CN2007101802315A CN101154461B (zh) 2000-09-28 2001-09-20 半导体存储装置
CNB2004100421793A CN100431045C (zh) 2000-09-28 2001-09-20 非易失半导体存储装置
US09/957,019 US6600676B2 (en) 2000-09-28 2001-09-21 Nonvolatile semiconductor memory device with a ROM block settable in the write or erase inhibit mode
US10/442,995 US6937512B2 (en) 2000-09-28 2003-05-22 Nonvolatile semiconductor memory device with a ROM block settable in the write or erase inhibit mode
US11/194,716 US7106627B2 (en) 2000-09-28 2005-08-02 Nonvolatile semiconductor memory device with redundancy and security information circuitry
US11/530,340 US7295469B2 (en) 2000-09-28 2006-09-08 Nonvolatile semiconductor memory device with a ROM block settable in a write/erase inhibit mode
US11/772,271 US7613046B2 (en) 2000-09-28 2007-07-02 Nonvolatile semiconductor memory device carrying out simultaneous programming of memory cells
US12/576,638 US7894259B2 (en) 2000-09-28 2009-10-09 Nonvolatile semiconductor memory device with first and second write sequences controlled by a command or an address
US13/012,030 US8189389B2 (en) 2000-09-28 2011-01-24 Nonvolatile semiconductor memory device with a voltage setting circuit for a step-up shift test
US13/471,143 US8885408B2 (en) 2000-09-28 2012-05-14 Nonvolatile semiconductor memory device for rendering the same in a busy state after inputting data therein

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000297443A JP4184586B2 (ja) 2000-09-28 2000-09-28 半導体記憶装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2007274261A Division JP4703624B2 (ja) 2007-10-22 2007-10-22 半導体記憶装置

Publications (3)

Publication Number Publication Date
JP2002109893A JP2002109893A (ja) 2002-04-12
JP2002109893A5 JP2002109893A5 (enrdf_load_stackoverflow) 2006-06-08
JP4184586B2 true JP4184586B2 (ja) 2008-11-19

Family

ID=18779560

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000297443A Expired - Lifetime JP4184586B2 (ja) 2000-09-28 2000-09-28 半導体記憶装置

Country Status (5)

Country Link
US (8) US6600676B2 (enrdf_load_stackoverflow)
JP (1) JP4184586B2 (enrdf_load_stackoverflow)
KR (1) KR100458411B1 (enrdf_load_stackoverflow)
CN (5) CN101154459B (enrdf_load_stackoverflow)
TW (1) TW543200B (enrdf_load_stackoverflow)

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5362545A (en) * 1993-03-24 1994-11-08 Tingley Daniel A Aligned fiber reinforcement panel for structural wood members
USRE40110E1 (en) * 1999-09-20 2008-02-26 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device for storing multivalued data
FR2810438B1 (fr) * 2000-06-19 2002-09-06 St Microelectronics Sa Circuit de detection d'usure
JP4184586B2 (ja) * 2000-09-28 2008-11-19 株式会社東芝 半導体記憶装置
DE10162308A1 (de) * 2001-12-19 2003-07-03 Philips Intellectual Property Verfahren und Anordnung zur Zugriffssteuerung auf EEPROMs sowie ein entsprechendes Computerprogrammprodukt und eine entsprechendes computerlesbares Speichermedium
JP2005108273A (ja) 2003-09-26 2005-04-21 Toshiba Corp 不揮発性半導体記憶装置
US7139864B2 (en) 2003-12-30 2006-11-21 Sandisk Corporation Non-volatile memory and method with block management system
JP4170952B2 (ja) 2004-01-30 2008-10-22 株式会社東芝 半導体記憶装置
US7009889B2 (en) * 2004-05-28 2006-03-07 Sandisk Corporation Comprehensive erase verification for non-volatile memory
US7336531B2 (en) * 2004-06-25 2008-02-26 Micron Technology, Inc. Multiple level cell memory device with single bit per cell, re-mappable memory block
KR100632946B1 (ko) * 2004-07-13 2006-10-12 삼성전자주식회사 불 휘발성 메모리 장치 및 그것의 프로그램 방법
US7272050B2 (en) * 2004-08-10 2007-09-18 Samsung Electronics Co., Ltd. Non-volatile memory device and erase method of the same
US7145816B2 (en) * 2004-08-16 2006-12-05 Micron Technology, Inc. Using redundant memory for extra features
US7298648B2 (en) * 2004-11-19 2007-11-20 Samsung Electronics Co., Ltd. Page buffer and multi-state nonvolatile memory device including the same
KR100648281B1 (ko) * 2005-01-14 2006-11-23 삼성전자주식회사 보안 리던던시 블록을 구비한 낸드 플래시 메모리 장치
EP1750278B1 (en) * 2005-07-28 2009-11-11 STMicroelectronics S.r.l. Method of programming a four-level flash memory device and a related page buffer
KR100630537B1 (ko) * 2005-08-09 2006-10-02 주식회사 하이닉스반도체 듀얼 페이지 프로그램 기능을 가지는 플래시 메모리 장치의페이지 버퍼 회로 및 그 프로그램 동작 방법
JP4991131B2 (ja) * 2005-08-12 2012-08-01 株式会社東芝 半導体記憶装置
JP4647446B2 (ja) * 2005-09-20 2011-03-09 富士通株式会社 半導体記憶装置
JP4846314B2 (ja) * 2005-09-22 2011-12-28 株式会社東芝 半導体記憶装置
KR100660544B1 (ko) * 2005-10-25 2006-12-22 삼성전자주식회사 신뢰성을 향상시킬 수 있는 플래시 메모리 장치
JP4455492B2 (ja) 2005-12-27 2010-04-21 株式会社東芝 不揮発性半導体記憶装置
KR100757411B1 (ko) * 2006-02-03 2007-09-11 삼성전자주식회사 옵션 퓨즈 회로를 이용한 반도체 메모리 장치의 전압재설정 회로 및 그 방법
US7453723B2 (en) 2006-03-01 2008-11-18 Micron Technology, Inc. Memory with weighted multi-page read
JP4976764B2 (ja) * 2006-07-05 2012-07-18 株式会社東芝 半導体記憶装置
US7369434B2 (en) * 2006-08-14 2008-05-06 Micron Technology, Inc. Flash memory with multi-bit read
US7701770B2 (en) * 2006-09-29 2010-04-20 Hynix Semiconductor Inc. Flash memory device and program method thereof
JP2008097696A (ja) * 2006-10-11 2008-04-24 Elpida Memory Inc 半導体装置
JP4871701B2 (ja) * 2006-11-02 2012-02-08 株式会社日立製作所 ストレージシステム
KR100801035B1 (ko) * 2006-12-14 2008-02-04 삼성전자주식회사 멀티 레벨 셀의 프로그램 방법, 페이지 버퍼 블록 및 이를포함하는 불휘발성 메모리 장치
JP2008192212A (ja) * 2007-02-01 2008-08-21 Spansion Llc 半導体装置およびその制御方法
JP5032155B2 (ja) * 2007-03-02 2012-09-26 株式会社東芝 不揮発性半導体記憶装置、及び不揮発性半導体記憶システム
US7916544B2 (en) 2008-01-25 2011-03-29 Micron Technology, Inc. Random telegraph signal noise reduction scheme for semiconductor memories
US20100180183A1 (en) * 2009-01-12 2010-07-15 Macronix International Co., Ltd. Circuit for reducing the read disturbance in memory
CN102081972B (zh) * 2009-11-27 2015-05-20 上海华虹集成电路有限责任公司 一种eeprom器件测试电路及其测试方法
JP2011138569A (ja) * 2009-12-25 2011-07-14 Toshiba Corp 不揮発性半導体記憶装置
JP2011150749A (ja) * 2010-01-20 2011-08-04 Toshiba Corp 不揮発性半導体記憶装置
CN105788638A (zh) * 2011-03-04 2016-07-20 瑞萨电子株式会社 半导体器件
JP2013229080A (ja) * 2012-04-26 2013-11-07 Toshiba Corp 半導体記憶装置および半導体記憶装置のテスト方法
US9111624B2 (en) * 2013-03-22 2015-08-18 Katsuyuki Fujita Semiconductor memory device
US20150078178A1 (en) * 2013-09-16 2015-03-19 Tachyon Networks Incorporated Software platform for implementation and control of satellite communication systems
KR102210520B1 (ko) * 2013-12-19 2021-02-02 삼성전자주식회사 비휘발성 메모리 장치 및 그것의 소거 방법
US9281027B1 (en) * 2014-10-10 2016-03-08 Arm Limited Test techniques in memory devices
US9817593B1 (en) 2016-07-11 2017-11-14 Sandisk Technologies Llc Block management in non-volatile memory system with non-blocking control sync system
CN106708592B (zh) * 2017-01-25 2021-12-03 北京鸿智电通科技有限公司 一种微控制器以及用于微控制器的代码烧录方法
KR102677512B1 (ko) * 2018-08-07 2024-06-24 삼성전자주식회사 안전 로직을 포함하는 장치
US11093164B2 (en) * 2019-08-27 2021-08-17 Micron Technology, Inc. Handling bad blocks generated during a block erase operation
CN115062352B (zh) * 2022-08-16 2022-12-02 湖南进芯电子科技有限公司 加密区域动态调节的数据处理方法、系统及电路结构

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960003526B1 (ko) * 1992-10-02 1996-03-14 삼성전자주식회사 반도체 메모리장치
US4571707A (en) * 1984-02-23 1986-02-18 Nec Corporation Memory circuit with improved redundant structure
JPS6141192A (ja) * 1984-07-31 1986-02-27 株式会社河合楽器製作所 楽音装置
US4933898A (en) 1989-01-12 1990-06-12 General Instrument Corporation Secure integrated circuit chip with conductive shield
US5127041A (en) * 1990-06-01 1992-06-30 Spectrum Information Technologies, Inc. System and method for interfacing computers to diverse telephone networks
US5394368A (en) 1991-08-28 1995-02-28 Oki Electric Industry Co., Ltd. Semiconductor memory device
US5406516A (en) * 1992-01-17 1995-04-11 Sharp Kabushiki Kaisha Semiconductor memory device
US5379415A (en) * 1992-09-29 1995-01-03 Zitel Corporation Fault tolerant memory system
JP2885597B2 (ja) * 1993-03-10 1999-04-26 株式会社東芝 半導体メモリ
US5363334A (en) 1993-04-10 1994-11-08 Microchip Technology Incorporated Write protection security for memory device
JPH07235198A (ja) 1994-02-18 1995-09-05 Fujitsu Ltd 半導体記憶装置
US5661694A (en) 1993-05-14 1997-08-26 Fujitsu Limited Programmable semiconductor memory device
US6026052A (en) 1994-05-03 2000-02-15 Fujitsu Limited Programmable semiconductor memory device
JP3476952B2 (ja) * 1994-03-15 2003-12-10 株式会社東芝 不揮発性半導体記憶装置
JP2914171B2 (ja) 1994-04-25 1999-06-28 松下電器産業株式会社 半導体メモリ装置およびその駆動方法
JPH07335509A (ja) 1994-06-03 1995-12-22 Hitachi Ltd 半導体集積回路装置
JP3263259B2 (ja) 1994-10-04 2002-03-04 株式会社東芝 半導体記憶装置
JPH10143434A (ja) 1996-11-11 1998-05-29 Toshiba Corp 半導体集積回路
KR19990061992A (ko) * 1997-12-31 1999-07-26 김영환 디램의 컬럼 리던던시 선택장치
JPH11232884A (ja) 1998-02-09 1999-08-27 Hitachi Ltd 不揮発性メモリ装置
US6223290B1 (en) * 1998-05-07 2001-04-24 Intel Corporation Method and apparatus for preventing the fraudulent use of a cellular telephone
JPH11328990A (ja) 1998-05-15 1999-11-30 Hitachi Ltd 半導体集積回路装置およびそれを用いたメモリカード
US6018483A (en) * 1998-12-10 2000-01-25 Siemens Aktiengesellschaft Distributed block redundancy for memory devices
US20010014036A1 (en) * 1998-12-21 2001-08-16 Karl Rapp Lock bit for an electrically erasable memory word
JP4463378B2 (ja) 2000-05-02 2010-05-19 富士通マイクロエレクトロニクス株式会社 不揮発性半導体記憶装置
JP4184586B2 (ja) * 2000-09-28 2008-11-19 株式会社東芝 半導体記憶装置
ITRM20030039A1 (it) * 2003-01-30 2004-07-31 Micron Technology Inc Sblocco di registro di protezione per chip.
JP5196965B2 (ja) * 2007-11-12 2013-05-15 株式会社東芝 不揮発性半導体記憶装置

Also Published As

Publication number Publication date
US7613046B2 (en) 2009-11-03
KR20020025711A (ko) 2002-04-04
US20070025149A1 (en) 2007-02-01
US7295469B2 (en) 2007-11-13
US7894259B2 (en) 2011-02-22
US20120224422A1 (en) 2012-09-06
US7106627B2 (en) 2006-09-12
US20110116315A1 (en) 2011-05-19
KR100458411B1 (ko) 2004-11-26
CN1346130A (zh) 2002-04-24
CN101154459B (zh) 2012-03-21
US20100027333A1 (en) 2010-02-04
US20020036930A1 (en) 2002-03-28
US8189389B2 (en) 2012-05-29
CN1540668A (zh) 2004-10-27
US6937512B2 (en) 2005-08-30
CN1178228C (zh) 2004-12-01
CN101154459A (zh) 2008-04-02
CN100431045C (zh) 2008-11-05
CN101154461A (zh) 2008-04-02
US20050265092A1 (en) 2005-12-01
TW543200B (en) 2003-07-21
US20070280017A1 (en) 2007-12-06
US20030206438A1 (en) 2003-11-06
US8885408B2 (en) 2014-11-11
CN101154461B (zh) 2011-10-19
CN101154465B (zh) 2011-10-05
US6600676B2 (en) 2003-07-29
CN101154465A (zh) 2008-04-02
JP2002109893A (ja) 2002-04-12

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