JP3938376B2 - テスト端子無効化回路 - Google Patents
テスト端子無効化回路 Download PDFInfo
- Publication number
- JP3938376B2 JP3938376B2 JP2004094572A JP2004094572A JP3938376B2 JP 3938376 B2 JP3938376 B2 JP 3938376B2 JP 2004094572 A JP2004094572 A JP 2004094572A JP 2004094572 A JP2004094572 A JP 2004094572A JP 3938376 B2 JP3938376 B2 JP 3938376B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- test
- invalidation
- signal
- nonvolatile memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- 238000012360 testing method Methods 0.000 title claims description 157
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 38
- 239000004065 semiconductor Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31701—Arrangements for setting the Unit Under Test [UUT] in a test mode
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Tests Of Electronic Circuits (AREA)
- Read Only Memory (AREA)
- Storage Device Security (AREA)
Description
101:テスト端子
102:スイッチ回路
103:テストモード信号発生回路
104:無効化信号発生回路
105:テスト信号制御回路
106:不揮発性メモリ回路
201:第1不揮発性メモリ素子
202:第2不揮発性メモリ素子
203:第1インバータ回路
204:第2インバータ回路
301:テスト端子
302:スイッチ回路
303:不揮発性メモリ回路
304:テストモード信号発生回路
400:本発明に係る不揮発性半導体記憶装置
401:テスト端子
402:本発明に係るテスト端子無効化回路
403:コントロール回路
404:不揮発性メモリ
500:本発明に係るICカード
501:テスト端子
502:本発明に係るテスト端子無効化回路
503:CPU
504:不揮発性メモリ
505:ROM
506:RAM
507:非接触用インタフェース回路
508:接触用インタフェース回路
509:マイコン
510:テスト端子
Claims (7)
- 1または複数のテスト端子から入力されるテスト信号を、そのまま有効な状態または所定の無効状態にしてテスト対象回路に対して出力するスイッチ回路と、
前記スイッチ回路に対してその出力信号の有効または無効状態を制御するテスト信号制御回路と、
テストモード時に前記テスト信号制御回路に対して、前記スイッチ回路の出力信号を有効状態とするテストモード信号を発生するテストモード信号発生回路と、
前記テスト信号制御回路に対して、前記スイッチ回路の出力信号を強制的に無効状態とする無効化信号を出力可能で、電気的に書き換え可能な不揮発性メモリ素子を用いて形成された無効化信号発生回路と、を備えてなり、
前記テスト信号制御回路は、前記無効化信号発生回路から前記無効化信号の入力を受け付けると、前記テストモード信号発生回路から前記テストモード信号の入力を受け付けても、前記スイッチ回路の出力信号を無効状態とすることを特徴とするテスト端子無効化回路。 - 前記無効化信号発生回路は、MOSFET構造の第1不揮発性メモリ素子と第2不揮発性メモリ素子、及び、第1インバータ回路と第2インバータ回路からなり、
前記第1不揮発性メモリ素子と前記第2不揮発性メモリ素子のソースが接地電圧に、前記第1不揮発性メモリ素子と前記第2不揮発性メモリ素子のゲートが電源電圧に、前記第1不揮発性メモリ素子のドレインが前記第1インバータ回路の入力と前記第2インバータ回路の出力に、前記第2不揮発性メモリ素子のドレインが前記第1インバータ回路の出力と前記第2インバータ回路の入力に、夫々接続され、
前記第1または第2インバータ回路の何れか一方の出力が前記無効化信号発生回路の出力となっていることを特徴とする請求項1に記載のテスト端子無効化回路。 - 前記無効化信号発生回路は、前記第1不揮発性メモリ素子と前記第2不揮発性メモリ素子の閾値電圧の差の大小に応じて、出力レベルが変化することを特徴とする請求項2に記載のテスト端子無効化回路。
- 請求項1〜3の何れか1項に記載のテスト端子無効化回路を用いたテスト信号無効化方法であって、
テスト終了後において、前記無効化信号発生回路の前記不揮発性メモリ素子に対する電気的な書き換え動作を行って前記無効化信号を出力させることを特徴とするテスト信号無効化方法。 - 請求項2または3に記載のテスト端子無効化回路を用いたテスト信号無効化方法であって、
テスト終了後において、前記無効化信号発生回路の前記第1または第2不揮発性メモリ素子の何れか一方に対して電気的な書き換え動作を行って前記無効化信号を出力させることを特徴とするテスト信号無効化方法。 - 請求項1〜3の何れか1項に記載のテスト端子無効化回路を備えていることを特徴とする不揮発性半導体記憶装置。
- 請求項6に記載の不揮発性半導体記憶装置を備えていることを特徴とするICカード。
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004094572A JP3938376B2 (ja) | 2004-03-29 | 2004-03-29 | テスト端子無効化回路 |
DE602005006340T DE602005006340T2 (de) | 2004-03-29 | 2005-03-16 | Prüfklemmen-Signalnegierschaltung |
EP05251585A EP1584936B1 (en) | 2004-03-29 | 2005-03-16 | Test terminal negation circuit |
AU2005201146A AU2005201146B2 (en) | 2004-03-29 | 2005-03-17 | Test terminal negation circuit |
KR1020050025508A KR100675247B1 (ko) | 2004-03-29 | 2005-03-28 | 테스트 단자 무효화 회로, 테스트 단자 무효화 방법, 불휘발성 반도체 기억 장치 및 ic 카드 |
CNB200510062467XA CN100405074C (zh) | 2004-03-29 | 2005-03-28 | 测试终端否定电路 |
US11/090,195 US7009879B2 (en) | 2004-03-29 | 2005-03-28 | Test terminal negation circuit for protecting data integrity |
TW094109851A TWI296374B (en) | 2004-03-29 | 2005-03-29 | Test terminal negation circuit, method of negating a test singal, nonvolatile semiconductor memory device, and ic card |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004094572A JP3938376B2 (ja) | 2004-03-29 | 2004-03-29 | テスト端子無効化回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005283208A JP2005283208A (ja) | 2005-10-13 |
JP3938376B2 true JP3938376B2 (ja) | 2007-06-27 |
Family
ID=34909425
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004094572A Expired - Fee Related JP3938376B2 (ja) | 2004-03-29 | 2004-03-29 | テスト端子無効化回路 |
Country Status (8)
Country | Link |
---|---|
US (1) | US7009879B2 (ja) |
EP (1) | EP1584936B1 (ja) |
JP (1) | JP3938376B2 (ja) |
KR (1) | KR100675247B1 (ja) |
CN (1) | CN100405074C (ja) |
AU (1) | AU2005201146B2 (ja) |
DE (1) | DE602005006340T2 (ja) |
TW (1) | TWI296374B (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8436638B2 (en) * | 2010-12-10 | 2013-05-07 | International Business Machines Corporation | Switch to perform non-destructive and secure disablement of IC functionality utilizing MEMS and method thereof |
EP3770796A1 (en) * | 2019-07-25 | 2021-01-27 | Mastercard International Incorporated | Method for hardware integrity control of an integrated circuit card |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1116395A (ja) * | 1997-06-25 | 1999-01-22 | Mitsubishi Electric Corp | 半導体記憶装置 |
JPH11353900A (ja) * | 1998-06-11 | 1999-12-24 | Mitsubishi Electric Corp | 半導体装置 |
JP3602984B2 (ja) * | 1999-07-09 | 2004-12-15 | 富士通株式会社 | メモリ装置 |
JP2001043140A (ja) * | 1999-08-03 | 2001-02-16 | Matsushita Electric Ind Co Ltd | メモリアクセス制御回路 |
JP4727785B2 (ja) * | 2000-01-26 | 2011-07-20 | 富士通セミコンダクター株式会社 | 半導体記憶装置及び半導体記憶装置のワード線欠陥検出方法 |
WO2001059571A2 (en) * | 2000-02-11 | 2001-08-16 | Advanced Micro Devices, Inc. | Command-driven test modes |
US6757832B1 (en) * | 2000-02-15 | 2004-06-29 | Silverbrook Research Pty Ltd | Unauthorized modification of values in flash memory |
JP4146618B2 (ja) * | 2001-03-09 | 2008-09-10 | 株式会社リコー | 光情報記録媒体およびその製造方法 |
JP3677215B2 (ja) * | 2001-03-13 | 2005-07-27 | 松下電器産業株式会社 | Icカード |
US6747905B1 (en) * | 2003-05-15 | 2004-06-08 | Ememory Technology Inc. | Voltage recovery switch |
-
2004
- 2004-03-29 JP JP2004094572A patent/JP3938376B2/ja not_active Expired - Fee Related
-
2005
- 2005-03-16 DE DE602005006340T patent/DE602005006340T2/de active Active
- 2005-03-16 EP EP05251585A patent/EP1584936B1/en active Active
- 2005-03-17 AU AU2005201146A patent/AU2005201146B2/en active Active
- 2005-03-28 US US11/090,195 patent/US7009879B2/en active Active
- 2005-03-28 CN CNB200510062467XA patent/CN100405074C/zh active Active
- 2005-03-28 KR KR1020050025508A patent/KR100675247B1/ko active IP Right Grant
- 2005-03-29 TW TW094109851A patent/TWI296374B/zh active
Also Published As
Publication number | Publication date |
---|---|
KR20060044846A (ko) | 2006-05-16 |
US20050213403A1 (en) | 2005-09-29 |
CN1677119A (zh) | 2005-10-05 |
TWI296374B (en) | 2008-05-01 |
DE602005006340D1 (de) | 2008-06-12 |
US7009879B2 (en) | 2006-03-07 |
DE602005006340T2 (de) | 2009-06-10 |
CN100405074C (zh) | 2008-07-23 |
JP2005283208A (ja) | 2005-10-13 |
EP1584936A1 (en) | 2005-10-12 |
KR100675247B1 (ko) | 2007-01-29 |
EP1584936B1 (en) | 2008-04-30 |
TW200538929A (en) | 2005-12-01 |
AU2005201146A1 (en) | 2005-10-13 |
AU2005201146B2 (en) | 2007-07-26 |
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