WO2001059571A2

WO2001059571A2 - Command-driven test modes

Info

Publication number: WO2001059571A2
Application number: PCT/US2001/040030
Authority: WO
Inventors: Jin-Lien Lin; Takao Akaogi; Ali K. Al-Shamma; Lee Edward Cleveland; Yong Kim; Boon Tang Teh; Kendra Nguyen
Original assignee: Advanced Micro Devices, Inc.; Fujitsu Limited
Priority date: 2000-02-11
Filing date: 2001-02-05
Publication date: 2001-08-16
Also published as: WO2001059571A3

Abstract

A system and a method for selectively placing a computer memory device (100), even when its data/address pins (104) are multiplexed, into a special test mode. In order to allow the manufacturer of a memory device to selectively enter into one of a plurality of special high-speed tests, while preventing an ordinary user of the memory device from accidentally entering into such test modes, a combination of one or more high voltage pins and a sequence of test-mode commands (303, 304) are used to selectively enter into a special test mode. The high voltage pin serves as an enable signal input to a test-mode command decoder (202) to enable it for receiving and recognizing a specific sequence of test-mode commands (303, 304). The specific sequence of test-mode commands (303, 304) is supplied to selectively put the memory device in one of a plurality of test modes.

Description

COMMAND-DRIVEN TEST MODES

BACKGROUND ART

Electronic systems typically include processors and memory The memory is used to store instructions and data In some systems, such as cellular phones, non-volatile memory is needed to ensure that the stored data is not lost even when the system is turned off One non-volatile memory family is Read Only Memory (ROM), Programmable ROM (PROM), and Erasable-Programmable ROM (EPROM), with varying degrees of flexibility of use ROM memories have high density, low power consumption, and high performance, but they are not m- system updateable On the other hand is the volatile memory family of Random Access Memory (RAM), Dynamic RAM (DRAM), and battery-backed Static RAM (SRAM) The RAM family, however, is in-system updateable and has high performance, but it is volatile DRAM stores temporary data, and SRAM integrates a battery to retain stored data when system powei is removed SRAM is considerably more expensive than DRAM Electrically- Erasable-Programmable ROM (EEPROM) is a special kind of ROM that is in-system modifiable on a byte-by-byte basis. like RAM, but it is also non-volatile, like ROM

Flash memoiy is one type of inherently nonvolatile memoiy, with no refresh or battery requirements, which can be erased or programmed in units of memory called blocks It is a variation oi EEPROM which, unlike flash memory, is erased and rewritten at the byte level which is slower than flash memory updating Flash memory is often used to hold control code such as BIOS in peisonal computer When BIOS needs to be changed, the flash memory can be updated in block (rather than byte) sizes, making it easy to update Flash memory is used in digital cellular phones, digital cameras LAN switches PC caids for notebook computeis, digital set-up boxes, embedded controllers, and other devices Flash memoiy is in-system updateable Its simpler cell architecture (only one transistor) gives it significant density advantages over both EEPROM and SRAM, and compares favorably with densities achieved by ROM and DRAM on analogous manufacturing processes Finally, flash memory is the only approach to satisfy the desired chaiacteπstics of nonvolatility, upgiadcability high density, and low cost

Memory devices usually need to be tested under special testing mode by the manufacturci , sy stem designer, or system analyst of the memory device However, the ordinary memory users and customers should be prevented from accidentally entenng into such special test modes A prior solution to making it difficult for an ordinary memory customer from accidentally entering into such special test modes has been to requii e a supply of high voltage to several address and/or control pins in order to selectively enter into a desired test mode Howevei this solution has several drawbacks First, in Older to detect the presence of a high voltage on several pins additional circuitiy is required at these pins This additional circuitiy adds undesired load to the pins, and thus slows down the overall operation of the memoiy device Second, this additional circuitry adds to the memory chip die size Third the prior solution of supplying high voltage on the addiess pins is not applicable in a multiplexed data/address pins system because no high voltage may be applied to a data pin

Therefore, there is a need for a high-speed test-mode generator that overcomes the above problems DISCLOSURE OF INVENTION

A system and a method that allows the manufacturer of a computer memory device to selectively place a memory unit into one of a plurality of special high-speed test modes, while making it difficult for an ordinary user of the memory device to accidentally enter into such test modes are provided A combination of one or more high-voltage pins and a sequence of test-mode commands are used to selectively enter into a special test mode The high voltage is used to generate an enable signal input to a test-mode command sequence decoder to enable it for receiving and recognizing a specific sequence of test mode commands The specific sequence of test-mode commands is supplied to the test-mode command decoder to generate test-mode signals that selectively put the memory device into the test mode corresponding to the supplied test-mode command sequence

The foregoing discussion of the present embodiments has been provided only by way of introduction Nothing in this section should be taken as a limitation on the lollowing claims, which define the scope of the invention

BRIEF DESCRIPTION OF DRAWINGS

FIG 1 is a block diagram of a memory device according to one aspect of this invention, FIG 2 is a block diagram of the test-mode generator of FIG 1 , FIG 3 is a timing diagram illustrating the operation of the FIG 2, FIG 4 is a circuit diagram of the high voltage detector of FIG 2, FIG 5 is a circuit diagram of the command decoder of FIG 2,

FIG 6 is a timing diagram illustrating the operation of the FIG 5

MODE(S0 FOR CARRYING OUT THE INVENTION

Referring to FIG 1 , it shows a block diagram of a memory device 100 The memory device 100 includes a memory element 101 , a command-driven test mode signal generator 102, and a controller/state machine 106

The memory element 101 may be any type of memory, such as flash memory, which may be arranged as an array of memory cells in a predetermined number of columns and rows The command-driven test-mode signal generator 102, as described in more details in the following in reference to FIGs 2-6, receives high voltage, placed by the controller/state machine 106 on one or more memory control pιnsl0 , and a sequence of commands also placed by the controller/state machine 106 on the memory data pins 104 The command-driven test-mode signal generator 102 then generates the test- mode signals 105 input to the memory element 101 to selectively place the latter in a desired test mode

In one aspect of the present invention the high voltage is applied to one or more memory control pins, and the sequence of commands is applied to the memory address or data pins In another aspect of the present invention, where the memory address and control pins are multiplexed to reduce the number of memory pins, the high voltage is applied to one or more control pins, and the sequence of commands is applied to the memory address/data pins Yet in another aspect of the present invention, the high voltage is applied to only one control pin

Referring now to FIG 2, it shows a block diagram of a command driven test-mode signal generator 200 The command-driven test mode signal generator 200 includes a high voltage detector 201 and a test-mode command decoder 202 In one aspect of this invention, the high voltage is applied only on the "Write Protect^*' memory control pin 203, although the high voltage may be applied to any one of the memory control pins, such as "Write Enable", "Chip Enable", etc After detecting a high voltage, such as 9 volts as compared to Vcc ol 1 8 volts, on the Write Protect control pin 203, the High Voltage (HV) Enable signal 204 line input to the test-mode command decoder 202 is activated Following the activation of the HV Enable signal, the controller/state machine supplies a specific sequence of test mode commands on the data pins 205 input to the test mode command decoder 202, through a sequence of command write cycles If the test-mode command decoder 202 receives a proper sequence of test mode commands, it decodes the address lines 208 and generates the test-mode signals SA(5 0) 206 that put the memory unit 101 into a desired one of a plurality of test modes which corresponds to (he test mode command sequence supplied to the command decoder 202

One aspect of the present invention is further described in reference to FIG 3, which shows a timing diagram of how the application of a high voltage on Write Protect control pin 203 and a sequence of two test mode commands 303, 304 on data lines 205 latch the memory inlo a desired test mode When the high voltage detector 201 detects a high voltage VHH on the Write Protect control pin 203, it activates the HV Enable signal line 204 Following the HV Enable signal line going high, a sequence of write cycles 303, 304 is supplied to the test-mode command decoder 202 to put the memory device into a desired lest mode Each test mode is characterized by a specific sequence of test mode commands, which is supplied to the decoder 202 through a specific number of write cycles Following the detection of a proper test-mode command sequence the memoiy device is selectively placed into the coπesponding specific test mode In one aspect of this invention, a test-mode command sequence consists of two write cycles 303, 304 as illustrated in the timing diagram of FIG 3 The first write cycle 303 may consist of a data DO (HEX) at a "don t care" address, and the second write cycle 304 may consist of data DO (Hex) at an address from 00 (HEX) to 1 l (HEX), depending on what test mode is efied When these two data are written into the test-mode decoder 202, following a high voltage on the Write Protect memory control pin 203, the decoder 202 recognizes the corresponding test mode and places the memoiy unit 101 in that test mode Once entered in a test mode it may be exited by eithei resetting the memory device or by removing the high voltage from the Write Protect control pin 203

FIG 4 shows a circuit diagram 400 for implementing the high voltage detector 201 of FIG 2. according to one aspect of this invention FIG 4 includes two P-channel MOSFETs 410, 41 1 nine N-channel MOSFETs

401 , 402, 403, 404, 405. 405, 406, 407, 408, 409, and two inverters 412 413 When a high voltage is detected on the Write Protect control signal 203 MOSFET 401 is turned on which subsequently turns on MOSFETs 410 and 403 When the voltage at node "c" gets highei than the voltage at node "d," the voltage at node ' g is pulled down to ground voltage Then the inverter 412 brings the HV Enable signal line 204 to high, as illustrated respectively, by the timing diagrams 203 and 204 of FIG 3 The low threshold MOSFETs 405-407 constitute a pull down path for the node "d," and t le MOSFET 402 is a high voltage protection mechanism

FIG 5 shows a circuit diagra n 500 ior implementing the test-mode command decoder 202 of FIG 2, accoiding to one aspect of the present lm cntion FIG 5 includes the shift registers 510, 51 1 , 512, 513, NAND gates 515 NOR gates 18, and Inverters 523 When the HV Enable signal 204 is activated, after Write Protect control pin 203 is detected with the high voltage value, the data lines IN (7 0) 205 are used to write a sequence of two write commands 303 and 304 into the command decoder 202 The address lines (5 0) 208 also are decoded to generate the test-mode signals SA(5 0) 206 which specify the desired lest mode

A more detailed disclosure of how the circuit of FIG 5 operates is presented in reference to the timing diagram of FIG 6 During the first write command cycle 303, at the first leading edge of the memory Write Enable signal WEXB 502, the signal at the output of the shift register 510, CLKX 504, is activated The activation of CLKX clocks the data IND0 501 through the shift register 51 1 At this stale CLK I is high and CLK 2 is low, causing the first latch of the address UA(5 0) 208 into the shift register 51 Ailerwards, during the second write command 304, at the second leading edge of the memory Write Enable signal WEXB 502, the output of the shift register 512, OUT 506, is activated This activation ot OUT signal causes the CLK I signal to go down and hence to latch the address UA (5 0) At the same time, the activation of OUT signal causes the CLK2 signal to go high and hence to pass the address lines UA (5 0) to the test mode signal lines SA(5 0) In the meantime, TMEN 507 signal goes high to indicate that the desired test mode is entered It further disables the clock input to the shift register 512 to prevent receiving any further input data during the present test mode condition

Therefore, a combination of a high voltage one memory control line and a specific sequence of test mode commands on address/data lines prevents an ordinary customer from accidentally entering into a test mode which is specially provided for the manufacture and system designers/analysts of the memory device

While a particular embodiment of the present invention has been shown and described, modifications may be made Furthermore, the inventive concept described herein may be applied to circuits other than memory devices It is, therefore, intended in the appended claims to cover all such changes and modifications, which fall within the true spirit and scope of the invention

Claims

What is claimed is

1 A method of entering a computer memory unit into a test mode, the method comprising of

(a) detecting a high voltage on one or more memory pins,

(b) recognizing a sequence of test-mode commands following said act in (a), and

(c) entering said memory unit into a test mode that corresponds to said sequence of lest mode commands

2 The method of claim 1 wherein said act in (a) comprises detecting a high voltage on one or more memory control pins

3 The method of claim 1 wherein said act in (a) comprises detecting a high voltage on one or more control pins of said memory device with multiplexed address and data pins

4 The method of claim 1 wherein said act in (a) comprises detecting a high voltage on a single control pin of said memory device

5 The method of claim 4 wherein said act in (b) comprises recognizing a sequence of two test mode commands

6 A system for entering a computer memory unit into a test mode, the system comprising

(a) a high-voltage detector, and

(b) a test-mode command decoder

7 The system of claim 6 wherein said one or more memory pins arc control pins

8 The system of claim 7 wherein the memory device includes address and data pins that are multiplexed

9 The system of claim 6 wherein only one memory control pin is provided with high voltage

10 The system of claim 9 wherein said sequence includes two test-mode commands

1 1 A system for entering a computer memory unit into a test mode, the system comprising of

(a) means for detecting a high voltage on one or more memory pins,

(b) means for recognizing a sequence of test-mode commands, and

(c) means for entering said memory unit into a test mode that corresponds to said sequence of test-mode commands

12. The system of claim 1 1 wherein said means in (a) comprises means for detecting a high voltage on one or more memory control pins.

13. The system of claim 1 1 wherein said means in (a) comprises means for detecting a high voltage on one or more control pins of said memory device with multiplexed address and data pins.

14. The system of claim 1 1 wherein said means in (a) comprises means for detecting a high voltage on a single control pin of said memory device.

15. The system of claim 14 wherein said means in (b) comprises means for detecting a sequence of two test- mode commands.