JP3883087B2 - 半導体記憶装置及び半導体メモリ回路 - Google Patents

半導体記憶装置及び半導体メモリ回路 Download PDF

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Publication number
JP3883087B2
JP3883087B2 JP31797798A JP31797798A JP3883087B2 JP 3883087 B2 JP3883087 B2 JP 3883087B2 JP 31797798 A JP31797798 A JP 31797798A JP 31797798 A JP31797798 A JP 31797798A JP 3883087 B2 JP3883087 B2 JP 3883087B2
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Japan
Prior art keywords
signal
circuit
test mode
command
semiconductor memory
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Expired - Fee Related
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JP31797798A
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Japanese (ja)
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JP2000149600A5 (enExample
JP2000149600A (ja
Inventor
直治 篠▲崎▼
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Fujitsu Ltd
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Fujitsu Ltd
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Priority to JP31797798A priority Critical patent/JP3883087B2/ja
Priority to US09/385,006 priority patent/US6256240B1/en
Priority to KR1019990036293A priority patent/KR100571739B1/ko
Publication of JP2000149600A publication Critical patent/JP2000149600A/ja
Publication of JP2000149600A5 publication Critical patent/JP2000149600A5/ja
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/46—Test trigger logic

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  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Tests Of Electronic Circuits (AREA)
JP31797798A 1998-11-09 1998-11-09 半導体記憶装置及び半導体メモリ回路 Expired - Fee Related JP3883087B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP31797798A JP3883087B2 (ja) 1998-11-09 1998-11-09 半導体記憶装置及び半導体メモリ回路
US09/385,006 US6256240B1 (en) 1998-11-09 1999-08-27 Semiconductor memory circuit
KR1019990036293A KR100571739B1 (ko) 1998-11-09 1999-08-30 반도체 기억 장치

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31797798A JP3883087B2 (ja) 1998-11-09 1998-11-09 半導体記憶装置及び半導体メモリ回路

Publications (3)

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JP2000149600A JP2000149600A (ja) 2000-05-30
JP2000149600A5 JP2000149600A5 (enExample) 2004-12-02
JP3883087B2 true JP3883087B2 (ja) 2007-02-21

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JP31797798A Expired - Fee Related JP3883087B2 (ja) 1998-11-09 1998-11-09 半導体記憶装置及び半導体メモリ回路

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US (1) US6256240B1 (enExample)
JP (1) JP3883087B2 (enExample)
KR (1) KR100571739B1 (enExample)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001243797A (ja) 2000-02-29 2001-09-07 Fujitsu Ltd 半導体装置及びその試験方法
JP3569232B2 (ja) * 2001-01-17 2004-09-22 Ｎｅｃマイクロシステム株式会社 シリアルアクセス機能付きアドレスマルチプレクサメモリのテスト方式
JP3737437B2 (ja) 2001-02-01 2006-01-18 Ｎｅｃエレクトロニクス株式会社 半導体メモリ及びその動作モードのエントリー方法
JP4707255B2 (ja) * 2001-04-26 2011-06-22 ルネサスエレクトロニクス株式会社 半導体記憶装置
KR100800132B1 (ko) * 2001-09-13 2008-02-01 주식회사 하이닉스반도체 반도체 메모리 장치의 테스트 모드 엔트리 방법 및 이를 이용한 테스트 모드 신호선이 배치된 반도체 메모리 장치
US6914849B2 (en) * 2003-10-16 2005-07-05 International Business Machines Corporation Method and apparatus for reducing power consumption in a memory array with dynamic word line driver/decoders
KR100735575B1 (ko) * 2004-06-11 2007-07-04 삼성전자주식회사 메모리의 테스트 모드 인터페이스 방법 및 장치
KR100724626B1 (ko) * 2005-08-29 2007-06-04 주식회사 하이닉스반도체 테스트 모드 제어 회로
JP4778321B2 (ja) * 2006-01-30 2011-09-21 富士通セミコンダクター株式会社 半導体メモリ、メモリシステム
US8125243B1 (en) 2007-03-12 2012-02-28 Cypress Semiconductor Corporation Integrity checking of configurable data of programmable device
US8060661B1 (en) 2007-03-27 2011-11-15 Cypress Semiconductor Corporation Interface circuit and method for programming or communicating with an integrated circuit via a power supply pin
KR100902048B1 (ko) * 2007-05-14 2009-06-15 주식회사 하이닉스반도체 반도체 장치의 어드레스 수신회로
US7937631B2 (en) * 2007-08-28 2011-05-03 Qimonda Ag Method for self-test and self-repair in a multi-chip package environment
KR100891304B1 (ko) 2007-09-10 2009-04-06 주식회사 하이닉스반도체 테스트 모드 회로를 포함하는 반도체 메모리 장치
US20110004703A1 (en) * 2009-07-02 2011-01-06 Nanya Technology Corporation Illegal command handling
JP5514095B2 (ja) * 2010-12-24 2014-06-04 ルネサスエレクトロニクス株式会社 半導体記憶装置
KR101187642B1 (ko) * 2011-05-02 2012-10-08 에스케이하이닉스 주식회사 집적 회로의 모니터링 장치
JP5963647B2 (ja) * 2012-01-30 2016-08-03 エスアイアイ・セミコンダクタ株式会社 半導体記憶回路を備えた半導体装置
KR20170076098A (ko) * 2015-12-24 2017-07-04 에스케이하이닉스 주식회사 테스트 모드 제어 장치
CN115206409B (zh) * 2022-07-08 2025-08-01 长鑫存储技术有限公司 模式控制结构、测试模式控制方法及存储器

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62250593A (ja) * 1986-04-23 1987-10-31 Hitachi Ltd ダイナミツク型ｒａｍ
US5825782A (en) * 1996-01-22 1998-10-20 Micron Technology, Inc. Non-volatile memory system including apparatus for testing memory elements by writing and verifying data patterns

Also Published As

Publication number Publication date
US6256240B1 (en) 2001-07-03
JP2000149600A (ja) 2000-05-30
KR20000034911A (ko) 2000-06-26
KR100571739B1 (ko) 2006-04-18

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