JP3856544B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP3856544B2
JP3856544B2 JP29723097A JP29723097A JP3856544B2 JP 3856544 B2 JP3856544 B2 JP 3856544B2 JP 29723097 A JP29723097 A JP 29723097A JP 29723097 A JP29723097 A JP 29723097A JP 3856544 B2 JP3856544 B2 JP 3856544B2
Authority
JP
Japan
Prior art keywords
semiconductor device
film
contact
wiring
sidewall
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP29723097A
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English (en)
Japanese (ja)
Other versions
JPH11135746A5 (https=
JPH11135746A (ja
Inventor
和朗 冨田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP29723097A priority Critical patent/JP3856544B2/ja
Priority to TW087104068A priority patent/TW459280B/zh
Priority to US09/061,060 priority patent/US6023083A/en
Priority to KR1019980018300A priority patent/KR100272989B1/ko
Priority to DE19826689A priority patent/DE19826689B4/de
Priority to CN98116150A priority patent/CN1104037C/zh
Publication of JPH11135746A publication Critical patent/JPH11135746A/ja
Priority to US09/460,764 priority patent/US6284618B1/en
Priority to US09/843,728 priority patent/US6344406B2/en
Publication of JPH11135746A5 publication Critical patent/JPH11135746A5/ja
Application granted granted Critical
Publication of JP3856544B2 publication Critical patent/JP3856544B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/038—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers covering conductive structures
    • H10W20/039—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers covering conductive structures also covering sidewalls of the conductive structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H10W20/0633—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material using subtractive patterning of the conductive members

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP29723097A 1997-10-29 1997-10-29 半導体装置及びその製造方法 Expired - Fee Related JP3856544B2 (ja)

Priority Applications (8)

Application Number Priority Date Filing Date Title
JP29723097A JP3856544B2 (ja) 1997-10-29 1997-10-29 半導体装置及びその製造方法
TW087104068A TW459280B (en) 1997-10-29 1998-03-19 Semiconductor device and manufacturing method thereof
US09/061,060 US6023083A (en) 1997-10-29 1998-04-16 Semiconductor device having a conductor pattern side face provided with a separate conductive sidewall
KR1019980018300A KR100272989B1 (ko) 1997-10-29 1998-05-21 반도체 장치 및 그 제조 방법
DE19826689A DE19826689B4 (de) 1997-10-29 1998-06-16 Halbleiterbauelement und Herstellungsverfahren eines Halbleiterbauelementes
CN98116150A CN1104037C (zh) 1997-10-29 1998-07-22 半导体器件及其制造方法
US09/460,764 US6284618B1 (en) 1997-10-29 1999-12-14 Method of making a semiconductor device having a conductor pattern side face provided with a separate conductive sidewall
US09/843,728 US6344406B2 (en) 1997-10-29 2001-04-30 Method for manufacturing a semiconductor device having a conductor pattern side face provided with a separate conductive sidewall

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29723097A JP3856544B2 (ja) 1997-10-29 1997-10-29 半導体装置及びその製造方法

Publications (3)

Publication Number Publication Date
JPH11135746A JPH11135746A (ja) 1999-05-21
JPH11135746A5 JPH11135746A5 (https=) 2004-12-24
JP3856544B2 true JP3856544B2 (ja) 2006-12-13

Family

ID=17843859

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29723097A Expired - Fee Related JP3856544B2 (ja) 1997-10-29 1997-10-29 半導体装置及びその製造方法

Country Status (6)

Country Link
US (3) US6023083A (https=)
JP (1) JP3856544B2 (https=)
KR (1) KR100272989B1 (https=)
CN (1) CN1104037C (https=)
DE (1) DE19826689B4 (https=)
TW (1) TW459280B (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6268661B1 (en) * 1999-08-31 2001-07-31 Nec Corporation Semiconductor device and method of its fabrication
US6074943A (en) * 1997-04-16 2000-06-13 Texas Instruments Incorporated Sidewalls for guiding the via etch
US6278152B1 (en) * 1997-06-27 2001-08-21 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
JP3856544B2 (ja) 1997-10-29 2006-12-13 株式会社ルネサステクノロジ 半導体装置及びその製造方法
JPH11186382A (ja) * 1997-12-19 1999-07-09 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP2001036036A (ja) 1999-07-21 2001-02-09 Mitsubishi Electric Corp 半導体装置およびその製造方法
KR100558005B1 (ko) * 2003-11-17 2006-03-06 삼성전자주식회사 적어도 하나의 스토리지 노드를 갖는 반도체 장치들 및 그제조 방법들

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5331116A (en) * 1992-04-30 1994-07-19 Sgs-Thomson Microelectronics, Inc. Structure and method for forming contact structures in integrated circuits
KR970007967B1 (en) * 1994-05-11 1997-05-19 Hyundai Electronics Ind Fabrication method and semiconductor device
KR100211070B1 (ko) * 1994-08-19 1999-07-15 아끼구사 나오유끼 반도체 장치 및 그 제조방법
JPH08250589A (ja) 1995-03-14 1996-09-27 Sony Corp 半導体装置の製造方法
JP2679671B2 (ja) * 1995-03-30 1997-11-19 日本電気株式会社 半導体記憶装置の容量素子の製造方法
JPH08306664A (ja) 1995-05-10 1996-11-22 Sony Corp 半導体装置の製造方法
US5759911A (en) * 1995-08-22 1998-06-02 International Business Machines Corporation Self-aligned metallurgy
US5550076A (en) * 1995-09-11 1996-08-27 Vanguard International Semiconductor Corp. Method of manufacture of coaxial capacitor for dram memory cell and cell manufactured thereby
JP3012187B2 (ja) * 1996-02-05 2000-02-21 松下電子工業株式会社 半導体装置の製造方法
JP2790110B2 (ja) * 1996-02-28 1998-08-27 日本電気株式会社 半導体装置の製造方法
JP2795252B2 (ja) * 1996-02-29 1998-09-10 日本電気株式会社 半導体装置の製造方法
US5710074A (en) * 1996-10-18 1998-01-20 Vanguard International Semiconductor Corporation Increased surface area of an STC structure via the use of a storage node electrode comprised of polysilicon mesas and polysilicon sidewall spacers
US5710075A (en) * 1996-11-06 1998-01-20 Vanguard International Semiconductor Corporation Method to increase surface area of a storage node electrode, of an STC structure, for DRAM devices
US5731130A (en) * 1996-11-12 1998-03-24 Vanguard International Semiconductor Corporation Method for fabricating stacked capacitors on dynamic random access memory cells
US5792692A (en) * 1997-08-18 1998-08-11 Chartered Semiconductor Manufacturing, Ltd. Method of fabricating a twin hammer tree shaped capacitor structure for a dram device
JP3856544B2 (ja) 1997-10-29 2006-12-13 株式会社ルネサステクノロジ 半導体装置及びその製造方法
JPH11176833A (ja) 1997-12-10 1999-07-02 Mitsubishi Electric Corp 半導体装置及びその製造方法
JPH11186382A (ja) 1997-12-19 1999-07-09 Mitsubishi Electric Corp 半導体装置及びその製造方法

Also Published As

Publication number Publication date
KR19990036498A (ko) 1999-05-25
US6023083A (en) 2000-02-08
US6284618B1 (en) 2001-09-04
CN1215910A (zh) 1999-05-05
CN1104037C (zh) 2003-03-26
DE19826689A1 (de) 1999-05-12
US20010023122A1 (en) 2001-09-20
TW459280B (en) 2001-10-11
DE19826689B4 (de) 2005-03-31
JPH11135746A (ja) 1999-05-21
KR100272989B1 (ko) 2000-12-01
US6344406B2 (en) 2002-02-05

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