TW459280B - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
TW459280B
TW459280B TW087104068A TW87104068A TW459280B TW 459280 B TW459280 B TW 459280B TW 087104068 A TW087104068 A TW 087104068A TW 87104068 A TW87104068 A TW 87104068A TW 459280 B TW459280 B TW 459280B
Authority
TW
Taiwan
Prior art keywords
film
contact
edge
layer
conductive
Prior art date
Application number
TW087104068A
Other languages
English (en)
Chinese (zh)
Inventor
Kazuo Tomita
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Application granted granted Critical
Publication of TW459280B publication Critical patent/TW459280B/zh

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/038—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers covering conductive structures
    • H10W20/039—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers covering conductive structures also covering sidewalls of the conductive structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/063—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material
    • H10W20/0633—Manufacture or treatment of conductive parts of the interconnections by forming conductive members before forming protective insulating material using subtractive patterning of the conductive members

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
TW087104068A 1997-10-29 1998-03-19 Semiconductor device and manufacturing method thereof TW459280B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29723097A JP3856544B2 (ja) 1997-10-29 1997-10-29 半導体装置及びその製造方法

Publications (1)

Publication Number Publication Date
TW459280B true TW459280B (en) 2001-10-11

Family

ID=17843859

Family Applications (1)

Application Number Title Priority Date Filing Date
TW087104068A TW459280B (en) 1997-10-29 1998-03-19 Semiconductor device and manufacturing method thereof

Country Status (6)

Country Link
US (3) US6023083A (https=)
JP (1) JP3856544B2 (https=)
KR (1) KR100272989B1 (https=)
CN (1) CN1104037C (https=)
DE (1) DE19826689B4 (https=)
TW (1) TW459280B (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6268661B1 (en) * 1999-08-31 2001-07-31 Nec Corporation Semiconductor device and method of its fabrication
US6074943A (en) * 1997-04-16 2000-06-13 Texas Instruments Incorporated Sidewalls for guiding the via etch
US6278152B1 (en) * 1997-06-27 2001-08-21 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
JP3856544B2 (ja) 1997-10-29 2006-12-13 株式会社ルネサステクノロジ 半導体装置及びその製造方法
JPH11186382A (ja) * 1997-12-19 1999-07-09 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP2001036036A (ja) 1999-07-21 2001-02-09 Mitsubishi Electric Corp 半導体装置およびその製造方法
KR100558005B1 (ko) * 2003-11-17 2006-03-06 삼성전자주식회사 적어도 하나의 스토리지 노드를 갖는 반도체 장치들 및 그제조 방법들

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5331116A (en) * 1992-04-30 1994-07-19 Sgs-Thomson Microelectronics, Inc. Structure and method for forming contact structures in integrated circuits
KR970007967B1 (en) * 1994-05-11 1997-05-19 Hyundai Electronics Ind Fabrication method and semiconductor device
KR100211070B1 (ko) * 1994-08-19 1999-07-15 아끼구사 나오유끼 반도체 장치 및 그 제조방법
JPH08250589A (ja) 1995-03-14 1996-09-27 Sony Corp 半導体装置の製造方法
JP2679671B2 (ja) * 1995-03-30 1997-11-19 日本電気株式会社 半導体記憶装置の容量素子の製造方法
JPH08306664A (ja) 1995-05-10 1996-11-22 Sony Corp 半導体装置の製造方法
US5759911A (en) * 1995-08-22 1998-06-02 International Business Machines Corporation Self-aligned metallurgy
US5550076A (en) * 1995-09-11 1996-08-27 Vanguard International Semiconductor Corp. Method of manufacture of coaxial capacitor for dram memory cell and cell manufactured thereby
JP3012187B2 (ja) * 1996-02-05 2000-02-21 松下電子工業株式会社 半導体装置の製造方法
JP2790110B2 (ja) * 1996-02-28 1998-08-27 日本電気株式会社 半導体装置の製造方法
JP2795252B2 (ja) * 1996-02-29 1998-09-10 日本電気株式会社 半導体装置の製造方法
US5710074A (en) * 1996-10-18 1998-01-20 Vanguard International Semiconductor Corporation Increased surface area of an STC structure via the use of a storage node electrode comprised of polysilicon mesas and polysilicon sidewall spacers
US5710075A (en) * 1996-11-06 1998-01-20 Vanguard International Semiconductor Corporation Method to increase surface area of a storage node electrode, of an STC structure, for DRAM devices
US5731130A (en) * 1996-11-12 1998-03-24 Vanguard International Semiconductor Corporation Method for fabricating stacked capacitors on dynamic random access memory cells
US5792692A (en) * 1997-08-18 1998-08-11 Chartered Semiconductor Manufacturing, Ltd. Method of fabricating a twin hammer tree shaped capacitor structure for a dram device
JP3856544B2 (ja) 1997-10-29 2006-12-13 株式会社ルネサステクノロジ 半導体装置及びその製造方法
JPH11176833A (ja) 1997-12-10 1999-07-02 Mitsubishi Electric Corp 半導体装置及びその製造方法
JPH11186382A (ja) 1997-12-19 1999-07-09 Mitsubishi Electric Corp 半導体装置及びその製造方法

Also Published As

Publication number Publication date
KR19990036498A (ko) 1999-05-25
US6023083A (en) 2000-02-08
US6284618B1 (en) 2001-09-04
CN1215910A (zh) 1999-05-05
CN1104037C (zh) 2003-03-26
DE19826689A1 (de) 1999-05-12
US20010023122A1 (en) 2001-09-20
JP3856544B2 (ja) 2006-12-13
DE19826689B4 (de) 2005-03-31
JPH11135746A (ja) 1999-05-21
KR100272989B1 (ko) 2000-12-01
US6344406B2 (en) 2002-02-05

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GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees