JP3761481B2 - 同期回路 - Google Patents

同期回路 Download PDF

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Publication number
JP3761481B2
JP3761481B2 JP2002085117A JP2002085117A JP3761481B2 JP 3761481 B2 JP3761481 B2 JP 3761481B2 JP 2002085117 A JP2002085117 A JP 2002085117A JP 2002085117 A JP2002085117 A JP 2002085117A JP 3761481 B2 JP3761481 B2 JP 3761481B2
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JP
Japan
Prior art keywords
signal
phase
clock
output
control signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2002085117A
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English (en)
Japanese (ja)
Other versions
JP2003283332A (ja
JP2003283332A5 (enExample
Inventor
晋一 吉岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2002085117A priority Critical patent/JP3761481B2/ja
Priority to TW092106527A priority patent/TWI255120B/zh
Priority to US10/395,057 priority patent/US6737896B2/en
Priority to CNB031082351A priority patent/CN1266873C/zh
Publication of JP2003283332A publication Critical patent/JP2003283332A/ja
Publication of JP2003283332A5 publication Critical patent/JP2003283332A5/ja
Application granted granted Critical
Publication of JP3761481B2 publication Critical patent/JP3761481B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
JP2002085117A 2002-03-26 2002-03-26 同期回路 Expired - Fee Related JP3761481B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2002085117A JP3761481B2 (ja) 2002-03-26 2002-03-26 同期回路
TW092106527A TWI255120B (en) 2002-03-26 2003-03-24 Synchronization circuit
US10/395,057 US6737896B2 (en) 2002-03-26 2003-03-25 Synchronous circuit
CNB031082351A CN1266873C (zh) 2002-03-26 2003-03-26 同步电路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002085117A JP3761481B2 (ja) 2002-03-26 2002-03-26 同期回路

Publications (3)

Publication Number Publication Date
JP2003283332A JP2003283332A (ja) 2003-10-03
JP2003283332A5 JP2003283332A5 (enExample) 2005-01-06
JP3761481B2 true JP3761481B2 (ja) 2006-03-29

Family

ID=28449244

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002085117A Expired - Fee Related JP3761481B2 (ja) 2002-03-26 2002-03-26 同期回路

Country Status (4)

Country Link
US (1) US6737896B2 (enExample)
JP (1) JP3761481B2 (enExample)
CN (1) CN1266873C (enExample)
TW (1) TWI255120B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100936201B1 (ko) * 2005-03-31 2010-01-11 후지쯔 가부시끼가이샤 클록 선택 회로 및 신시사이저

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI298223B (en) * 2002-11-04 2008-06-21 Mstar Semiconductor Inc Data recovery circuit, phase detection circuit and method for detecting and correcting phase conditions
CN1319309C (zh) * 2003-12-25 2007-05-30 华为技术有限公司 在同一系统上实现系统多时钟的方法及装置
TWI239717B (en) * 2004-05-04 2005-09-11 Novatek Microelectronics Co Analog front end with automatic sampling timing generation system and method thereof
JP4271623B2 (ja) 2004-06-17 2009-06-03 富士通株式会社 クロック調整装置および方法
US20060188046A1 (en) * 2005-02-24 2006-08-24 Broadcom Corporation Prediction of an optimal sampling point for clock resynchronization in a source synchronous data channel
US20060187729A1 (en) * 2005-02-24 2006-08-24 Broadcom Corporation Source synchronous communication channel interface receive logic
KR100649881B1 (ko) * 2005-06-02 2006-11-27 삼성전자주식회사 클락 신호들을 동기시키기 위한 반도체 장치 및 클락신호들을 동기시키는 방법
US7487378B2 (en) * 2005-09-19 2009-02-03 Ati Technologies, Inc. Asymmetrical IO method and system
CN100440773C (zh) * 2006-04-18 2008-12-03 威盛电子股份有限公司 相位内插收发电路及其收发方法
JP4359786B2 (ja) * 2007-03-22 2009-11-04 日本電気株式会社 データ伝送装置及びクロック切替回路
US7882474B2 (en) * 2008-03-17 2011-02-01 Avago Technologies Enterprise IP (Singapore) Pte. Ltd. Testing phase error of multiple on-die clocks
JP2009231896A (ja) * 2008-03-19 2009-10-08 Fujitsu Ltd 受信装置および受信方法
JP2009239768A (ja) * 2008-03-28 2009-10-15 Hitachi Ltd 半導体集積回路装置、及び、クロックデータ復元方法
JP2010074201A (ja) * 2008-09-16 2010-04-02 Nec Electronics Corp 同期検出回路、これを用いたパルス幅変調回路、及び同期検出方法
CN101917370B (zh) * 2010-08-10 2012-12-05 北京天碁科技有限公司 一种扩大解调数据的频偏估计范围的方法和装置
US8405533B2 (en) * 2010-12-15 2013-03-26 Intel Corporation Providing a feedback loop in a low latency serial interconnect architecture
JP6092727B2 (ja) 2012-08-30 2017-03-08 株式会社メガチップス 受信装置
US20150341040A1 (en) * 2012-12-28 2015-11-26 Xinfeng Quantel Technologies (Beijing) Co., Ltd Clock Generator and Switch-capacitor Circuit Comprising the Same
CN103078611B (zh) * 2012-12-28 2016-01-20 芯锋宽泰科技（北京）有限公司 时钟产生器以及包括其的开关电容电路
TW201445887A (zh) * 2013-05-23 2014-12-01 Raydium Semiconductor Corp 時脈嵌入式序列資料傳輸系統及時脈還原方法
US9613665B2 (en) * 2014-03-06 2017-04-04 Mediatek Inc. Method for performing memory interface control of an electronic device, and associated apparatus
CN104280613B (zh) * 2014-10-15 2017-03-08 成都振芯科技股份有限公司 一种片内信号间的相位检测与同步电路及其同步方法
CN112398767B (zh) * 2019-08-14 2024-04-02 瑞昱半导体股份有限公司 智能相位切换方法及智能相位切换系统

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4755704A (en) * 1987-06-30 1988-07-05 Unisys Corporation Automatic clock de-skewing apparatus
KR970002949B1 (ko) * 1994-05-25 1997-03-13 삼성전자 주식회사 디지탈 통신시스템의 클럭발생방법 및 그 회로
KR100194624B1 (ko) * 1996-12-02 1999-06-15 이계철 데이타 리타이밍 회로
JPH10239397A (ja) * 1997-02-27 1998-09-11 Ando Electric Co Ltd Ｉｃ試験装置
JP2001186111A (ja) 1999-12-24 2001-07-06 Nec Corp ビット同期回路

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100936201B1 (ko) * 2005-03-31 2010-01-11 후지쯔 가부시끼가이샤 클록 선택 회로 및 신시사이저

Also Published As

Publication number Publication date
US20030218483A1 (en) 2003-11-27
TWI255120B (en) 2006-05-11
TW200402220A (en) 2004-02-01
CN1447557A (zh) 2003-10-08
US6737896B2 (en) 2004-05-18
CN1266873C (zh) 2006-07-26
JP2003283332A (ja) 2003-10-03

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