JP3729849B2 - Eepromに薄いトンネル窓を形成するための方法 - Google Patents

Eepromに薄いトンネル窓を形成するための方法 Download PDF

Info

Publication number
JP3729849B2
JP3729849B2 JP50581295A JP50581295A JP3729849B2 JP 3729849 B2 JP3729849 B2 JP 3729849B2 JP 50581295 A JP50581295 A JP 50581295A JP 50581295 A JP50581295 A JP 50581295A JP 3729849 B2 JP3729849 B2 JP 3729849B2
Authority
JP
Japan
Prior art keywords
oxide layer
layer
oxide
substrate
nitride
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP50581295A
Other languages
English (en)
Japanese (ja)
Other versions
JPH08502630A (ja
Inventor
ラーセン,ブラッドレイ・ジェイ
エリクソン,ドナルド・エイ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atmel Corp
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Publication of JPH08502630A publication Critical patent/JPH08502630A/ja
Application granted granted Critical
Publication of JP3729849B2 publication Critical patent/JP3729849B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02538Group 13/15 materials
    • H01L21/0254Nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02551Group 12/16 materials
    • H01L21/02554Oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274Photolithographic processes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/68Floating-gate IGFETs
    • H10D30/681Floating-gate IGFETs having only two programming levels
    • H10D30/684Floating-gate IGFETs having only two programming levels programmed by hot carrier injection
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/117Oxidation, selective
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/163Thick-thin oxides
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/981Utilizing varying dielectric thickness

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
JP50581295A 1993-07-30 1994-06-17 Eepromに薄いトンネル窓を形成するための方法 Expired - Fee Related JP3729849B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/100,467 US5352618A (en) 1993-07-30 1993-07-30 Method for forming thin tunneling windows in EEPROMs
US100,467 1993-07-30
PCT/US1994/006860 WO1995004371A1 (en) 1993-07-30 1994-06-17 METHOD FOR FORMING THIN TUNNELING WINDOWS IN EEPROMs

Publications (2)

Publication Number Publication Date
JPH08502630A JPH08502630A (ja) 1996-03-19
JP3729849B2 true JP3729849B2 (ja) 2005-12-21

Family

ID=22279908

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50581295A Expired - Fee Related JP3729849B2 (ja) 1993-07-30 1994-06-17 Eepromに薄いトンネル窓を形成するための方法

Country Status (8)

Country Link
US (1) US5352618A (enExample)
EP (1) EP0664051B1 (enExample)
JP (1) JP3729849B2 (enExample)
KR (1) KR100297301B1 (enExample)
CN (1) CN1045348C (enExample)
DE (1) DE69418447T2 (enExample)
TW (1) TW248615B (enExample)
WO (1) WO1995004371A1 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5429960A (en) * 1994-11-28 1995-07-04 United Microelectronics Corporation Method of making flash EEPROM memory
US5521109A (en) * 1995-09-01 1996-05-28 United Microelectronics Corp. Method for fabricating a high coupling ratio flash memory with a very narrow tunnel layer
US5963806A (en) * 1996-12-09 1999-10-05 Mosel Vitelic, Inc. Method of forming memory cell with built-in erasure feature
US5895240A (en) * 1997-06-30 1999-04-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making stepped edge structure of an EEPROM tunneling window
US5918133A (en) * 1997-12-18 1999-06-29 Advanced Micro Devices Semiconductor device having dual gate dielectric thickness along the channel and fabrication thereof
US6255165B1 (en) * 1999-10-18 2001-07-03 Advanced Micro Devices, Inc. Nitride plug to reduce gate edge lifting
US6518072B1 (en) * 1999-11-05 2003-02-11 Advanced Micro Devices, Inc. Deposited screen oxide for reducing gate edge lifting
US20060073509A1 (en) * 1999-11-18 2006-04-06 Michael Kilpatrick Method for detecting and quantitating multiple subcellular components
US6624027B1 (en) 2002-05-09 2003-09-23 Atmel Corporation Ultra small thin windows in floating gate transistors defined by lost nitride spacers
US6905926B2 (en) * 2003-09-04 2005-06-14 Atmel Corporation Method of making nonvolatile transistor pairs with shared control gate
US7161203B2 (en) * 2004-06-04 2007-01-09 Micron Technology, Inc. Gated field effect device comprising gate dielectric having different K regions
US7553704B2 (en) * 2005-06-28 2009-06-30 Freescale Semiconductor, Inc. Antifuse element and method of manufacture
US7528015B2 (en) * 2005-06-28 2009-05-05 Freescale Semiconductor, Inc. Tunable antifuse element and method of manufacture
CN106816368B (zh) * 2015-12-01 2019-11-05 中芯国际集成电路制造(上海)有限公司 半导体结构和cmos晶体管的形成方法
CN114551452A (zh) * 2016-10-21 2022-05-27 联华电子股份有限公司 单层多晶硅电子抹除式可复写只读存储器

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4817561A (en) * 1986-12-17 1989-04-04 Ichthyotech, Ltd. Aquatic aeration and filtering system
US4755477A (en) * 1987-03-24 1988-07-05 Industrial Technology Research Institute Overhang isolation technology
JP2701332B2 (ja) 1988-07-08 1998-01-21 日本電気株式会社 浮遊ゲート型不揮発性半導体記憶装置の製造方法
US4941822A (en) * 1989-07-20 1990-07-17 Marvin Evans Apparatus for heat treating contaminated particulate material
CN2078413U (zh) * 1990-10-13 1991-06-05 福建省宁德市茶叶机械制造厂 连续反烧燃煤装置
US5216270A (en) * 1991-02-28 1993-06-01 Texas Instruments Incorporated Non-volatile memory cell with tunnel window structure and method
US5236862A (en) * 1992-12-03 1993-08-17 Motorola, Inc. Method of forming oxide isolation

Also Published As

Publication number Publication date
JPH08502630A (ja) 1996-03-19
TW248615B (enExample) 1995-06-01
EP0664051B1 (en) 1999-05-12
EP0664051A4 (en) 1996-01-10
US5352618A (en) 1994-10-04
KR950703209A (ko) 1995-08-23
CN1111466A (zh) 1995-11-08
EP0664051A1 (en) 1995-07-26
CN1045348C (zh) 1999-09-29
WO1995004371A1 (en) 1995-02-09
DE69418447T2 (de) 2000-01-05
DE69418447D1 (de) 1999-06-17
KR100297301B1 (ko) 2001-10-24

Similar Documents

Publication Publication Date Title
CN100435296C (zh) 多位非易失性存储器器件及其方法
US5411905A (en) Method of making trench EEPROM structure on SOI with dual channels
US6946346B2 (en) Method for manufacturing a single electron memory device having quantum dots between gate electrode and single electron storage element
JP3729849B2 (ja) Eepromに薄いトンネル窓を形成するための方法
US6017795A (en) Method of fabricating buried source to shrink cell dimension and increase coupling ratio in split-gate flash
CN100440514C (zh) 非易失浮栅存储单元及其阵列以及其形成方法
JPH05206479A (ja) フィールド分離領域に重なるトンネル開口部を有するeepromセル
US6284637B1 (en) Method to fabricate a floating gate with a sloping sidewall for a flash memory
US20040076050A1 (en) Flash memory cell with high programming efficiency by coupling from floating gate to sidewall
KR100439025B1 (ko) 플래쉬 메모리의 부유 전극의 형성 방법
US6166409A (en) Flash EPROM memory cell having increased capacitive coupling
US6174771B1 (en) Split gate flash memory cell with self-aligned process
US7443725B2 (en) Floating gate isolation and method of making the same
US20080182375A1 (en) Split gate memory cell method
KR100593599B1 (ko) 반도체 소자의 제조 방법
JP3274785B2 (ja) 不揮発性メモリの製造方法
JP2727136B2 (ja) 自己整合トンネル誘電体領域を有する電気的に消去可能かつ電気的にプログラム可能のメモリーデバイス及びその製法
KR100490654B1 (ko) 수직형이이피롬셀및그제조방법
KR19990055404A (ko) 이이피롬 셀 및 그 제조방법
KR100549346B1 (ko) 플래쉬 이이피롬의 제조 방법
KR100293642B1 (ko) 플래쉬 메모리 소자의 플로팅 게이트 형성 방법
KR0176178B1 (ko) 불휘발성 반도체 메모리 장치 및 그 제조방법
JP3439073B2 (ja) 不揮発性半導体記憶装置の製造方法
JPH05136425A (ja) 再結晶化浮動ゲートを有する電気的に変更可能な単一トランジスタ不揮発性半導体記憶装置

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20041116

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20050215

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20050404

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050513

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20050920

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20051005

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091014

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20091014

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101014

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111014

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121014

Year of fee payment: 7

LAPS Cancellation because of no payment of annual fees