KR100297301B1 - 이이피롬(eeprom)에박막의터널링윈도우를형성하는방법 - Google Patents

이이피롬(eeprom)에박막의터널링윈도우를형성하는방법 Download PDF

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Publication number
KR100297301B1
KR100297301B1 KR1019950700777A KR19950700777A KR100297301B1 KR 100297301 B1 KR100297301 B1 KR 100297301B1 KR 1019950700777 A KR1019950700777 A KR 1019950700777A KR 19950700777 A KR19950700777 A KR 19950700777A KR 100297301 B1 KR100297301 B1 KR 100297301B1
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KR
South Korea
Prior art keywords
oxide layer
layer
oxide
substrate
nitride
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019950700777A
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English (en)
Korean (ko)
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KR950703209A (ko
Inventor
브래들리제이.라센
도날드에이.에릭슨
Original Assignee
페레고스 조지, 마이크 로스
아트멜 코포레이숀
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Publication of KR950703209A publication Critical patent/KR950703209A/ko
Application granted granted Critical
Publication of KR100297301B1 publication Critical patent/KR100297301B1/ko
Anticipated expiration legal-status Critical
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02551—Group 12/16 materials
    • H01L21/02554—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H10D30/684—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/163—Thick-thin oxides
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/981—Utilizing varying dielectric thickness

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
KR1019950700777A 1993-07-30 1994-06-17 이이피롬(eeprom)에박막의터널링윈도우를형성하는방법 Expired - Fee Related KR100297301B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/100,467 US5352618A (en) 1993-07-30 1993-07-30 Method for forming thin tunneling windows in EEPROMs
US08/100467 1993-07-30
PCT/US1994/006860 WO1995004371A1 (en) 1993-07-30 1994-06-17 METHOD FOR FORMING THIN TUNNELING WINDOWS IN EEPROMs

Publications (2)

Publication Number Publication Date
KR950703209A KR950703209A (ko) 1995-08-23
KR100297301B1 true KR100297301B1 (ko) 2001-10-24

Family

ID=22279908

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950700777A Expired - Fee Related KR100297301B1 (ko) 1993-07-30 1994-06-17 이이피롬(eeprom)에박막의터널링윈도우를형성하는방법

Country Status (8)

Country Link
US (1) US5352618A (enExample)
EP (1) EP0664051B1 (enExample)
JP (1) JP3729849B2 (enExample)
KR (1) KR100297301B1 (enExample)
CN (1) CN1045348C (enExample)
DE (1) DE69418447T2 (enExample)
TW (1) TW248615B (enExample)
WO (1) WO1995004371A1 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5429960A (en) * 1994-11-28 1995-07-04 United Microelectronics Corporation Method of making flash EEPROM memory
US5521109A (en) * 1995-09-01 1996-05-28 United Microelectronics Corp. Method for fabricating a high coupling ratio flash memory with a very narrow tunnel layer
US5963806A (en) 1996-12-09 1999-10-05 Mosel Vitelic, Inc. Method of forming memory cell with built-in erasure feature
US5895240A (en) * 1997-06-30 1999-04-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making stepped edge structure of an EEPROM tunneling window
US5918133A (en) * 1997-12-18 1999-06-29 Advanced Micro Devices Semiconductor device having dual gate dielectric thickness along the channel and fabrication thereof
US6255165B1 (en) * 1999-10-18 2001-07-03 Advanced Micro Devices, Inc. Nitride plug to reduce gate edge lifting
US6518072B1 (en) * 1999-11-05 2003-02-11 Advanced Micro Devices, Inc. Deposited screen oxide for reducing gate edge lifting
US20060073509A1 (en) * 1999-11-18 2006-04-06 Michael Kilpatrick Method for detecting and quantitating multiple subcellular components
US6624027B1 (en) * 2002-05-09 2003-09-23 Atmel Corporation Ultra small thin windows in floating gate transistors defined by lost nitride spacers
US6905926B2 (en) * 2003-09-04 2005-06-14 Atmel Corporation Method of making nonvolatile transistor pairs with shared control gate
US7161203B2 (en) * 2004-06-04 2007-01-09 Micron Technology, Inc. Gated field effect device comprising gate dielectric having different K regions
US7528015B2 (en) * 2005-06-28 2009-05-05 Freescale Semiconductor, Inc. Tunable antifuse element and method of manufacture
US7553704B2 (en) * 2005-06-28 2009-06-30 Freescale Semiconductor, Inc. Antifuse element and method of manufacture
CN106816368B (zh) * 2015-12-01 2019-11-05 中芯国际集成电路制造(上海)有限公司 半导体结构和cmos晶体管的形成方法
CN107978601B (zh) * 2016-10-21 2022-02-22 联华电子股份有限公司 单层多晶硅电子抹除式可复写只读存储器

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4817561A (en) * 1986-12-17 1989-04-04 Ichthyotech, Ltd. Aquatic aeration and filtering system
US4755477A (en) * 1987-03-24 1988-07-05 Industrial Technology Research Institute Overhang isolation technology
JP2701332B2 (ja) 1988-07-08 1998-01-21 日本電気株式会社 浮遊ゲート型不揮発性半導体記憶装置の製造方法
US4941822A (en) * 1989-07-20 1990-07-17 Marvin Evans Apparatus for heat treating contaminated particulate material
CN2078413U (zh) * 1990-10-13 1991-06-05 福建省宁德市茶叶机械制造厂 连续反烧燃煤装置
US5216270A (en) * 1991-02-28 1993-06-01 Texas Instruments Incorporated Non-volatile memory cell with tunnel window structure and method
US5236862A (en) * 1992-12-03 1993-08-17 Motorola, Inc. Method of forming oxide isolation

Also Published As

Publication number Publication date
DE69418447T2 (de) 2000-01-05
TW248615B (enExample) 1995-06-01
CN1111466A (zh) 1995-11-08
EP0664051A1 (en) 1995-07-26
EP0664051A4 (en) 1996-01-10
CN1045348C (zh) 1999-09-29
EP0664051B1 (en) 1999-05-12
JP3729849B2 (ja) 2005-12-21
US5352618A (en) 1994-10-04
JPH08502630A (ja) 1996-03-19
DE69418447D1 (de) 1999-06-17
KR950703209A (ko) 1995-08-23
WO1995004371A1 (en) 1995-02-09

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