JP3574696B2 - Ｉｃテスタのタイミング発生器 - Google Patents

Ｉｃテスタのタイミング発生器 Download PDF

Info

Publication number
JP3574696B2
JP3574696B2 JP12788395A JP12788395A JP3574696B2 JP 3574696 B2 JP3574696 B2 JP 3574696B2 JP 12788395 A JP12788395 A JP 12788395A JP 12788395 A JP12788395 A JP 12788395A JP 3574696 B2 JP3574696 B2 JP 3574696B2
Authority
JP
Japan
Prior art keywords
data
delay
reset
delay means
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP12788395A
Other languages
English (en)
Japanese (ja)
Other versions
JPH08320360A (ja
Inventor
昌克 須田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Priority to JP12788395A priority Critical patent/JP3574696B2/ja
Priority to TW085105425A priority patent/TW296434B/zh
Priority to US08/652,344 priority patent/US5710744A/en
Priority to KR1019960018001A priority patent/KR100216415B1/ko
Publication of JPH08320360A publication Critical patent/JPH08320360A/ja
Application granted granted Critical
Publication of JP3574696B2 publication Critical patent/JP3574696B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31922—Timing generation or clock distribution
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Tests Of Electronic Circuits (AREA)
JP12788395A 1995-05-26 1995-05-26 Ｉｃテスタのタイミング発生器 Expired - Fee Related JP3574696B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP12788395A JP3574696B2 (ja) 1995-05-26 1995-05-26 Ｉｃテスタのタイミング発生器
TW085105425A TW296434B (enExample) 1995-05-26 1996-05-08
US08/652,344 US5710744A (en) 1995-05-26 1996-05-23 Timing generator for IC testers
KR1019960018001A KR100216415B1 (ko) 1995-05-26 1996-05-27 Ic 테스터의 타이밍 발생장치

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12788395A JP3574696B2 (ja) 1995-05-26 1995-05-26 Ｉｃテスタのタイミング発生器

Publications (2)

Publication Number Publication Date
JPH08320360A JPH08320360A (ja) 1996-12-03
JP3574696B2 true JP3574696B2 (ja) 2004-10-06

Family

ID=14971014

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12788395A Expired - Fee Related JP3574696B2 (ja) 1995-05-26 1995-05-26 Ｉｃテスタのタイミング発生器

Country Status (4)

Country Link
US (1) US5710744A (enExample)
JP (1) JP3574696B2 (enExample)
KR (1) KR100216415B1 (enExample)
TW (1) TW296434B (enExample)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6032282A (en) * 1994-09-19 2000-02-29 Advantest Corp. Timing edge forming circuit for IC test system
JP3690899B2 (ja) * 1997-05-30 2005-08-31 富士通株式会社 クロック発生回路及び半導体装置
US5867453A (en) * 1998-02-06 1999-02-02 Taiwan Semiconductor Manufacturing Co., Ltd. Self-setup non-overlap clock generator
US6304623B1 (en) * 1998-09-03 2001-10-16 Time Domain Corporation Precision timing generator system and method
US6172544B1 (en) * 1999-02-25 2001-01-09 Advantest Corp. Timing signal generation circuit for semiconductor test system
US6304119B1 (en) * 2000-12-27 2001-10-16 Chroma Ate Inc. Timing generating apparatus with self-calibrating capability
WO2003062843A1 (en) * 2002-01-18 2003-07-31 Advantest Corporation Tester
JP2003249923A (ja) * 2002-02-25 2003-09-05 Ando Electric Co Ltd ビットエラー測定装置及びそのトリガー信号発生回路
JP4657053B2 (ja) * 2005-07-29 2011-03-23 株式会社アドバンテスト タイミング発生器及び半導体試験装置
CN101473587A (zh) * 2006-06-16 2009-07-01 松下电器产业株式会社 数据发送装置和数据发送方法
JP4730611B2 (ja) * 2006-06-27 2011-07-20 横河電機株式会社 遅延時間測定方法及びこれを用いた遅延時間測定装置
JP5025723B2 (ja) * 2007-03-27 2012-09-12 株式会社アドバンテスト 試験装置
US8150648B2 (en) * 2008-12-26 2012-04-03 Advantest Corporation Timing generator
WO2010150303A1 (ja) 2009-06-22 2010-12-29 株式会社アドバンテスト タイミング発生器および試験装置
US8504320B2 (en) * 2009-08-10 2013-08-06 Advantest Corporation Differential SR flip-flop
JP2012138793A (ja) 2010-12-27 2012-07-19 Advantest Corp Ｓｒフリップフロップならびにそれを用いた試験装置
CN112711295B (zh) * 2019-10-25 2024-09-03 瑞昱半导体股份有限公司 时序产生器、时序产生方法以及控制芯片
US11500016B2 (en) * 2020-12-07 2022-11-15 Taiwan Semiconductor Manufacturing Company Ltd. Circuit screening system and circuit screening method

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5321700A (en) * 1989-10-11 1994-06-14 Teradyne, Inc. High speed timing generator
JP2854659B2 (ja) * 1990-03-20 1999-02-03 三菱電機株式会社 半導体装置のテスト装置
JP2590741Y2 (ja) * 1993-10-18 1999-02-17 株式会社アドバンテスト 半導体試験装置用タイミング発生器

Also Published As

Publication number Publication date
US5710744A (en) 1998-01-20
KR100216415B1 (ko) 1999-08-16
KR960042083A (ko) 1996-12-19
JPH08320360A (ja) 1996-12-03
TW296434B (enExample) 1997-01-21

Similar Documents

Publication Publication Date Title
JP3574696B2 (ja) Ｉｃテスタのタイミング発生器
US4675546A (en) Edge programmable timing signal generator
US7368967B2 (en) Timing controller and controlled delay circuit for controlling timing or delay time of a signal by changing phase thereof
KR100274901B1 (ko) 반도체집적회로
US5376849A (en) High resolution programmable pulse generator employing controllable delay
US5835970A (en) Burst address generator having two modes of operation employing a linear/nonlinear counter using decoded addresses
KR100256309B1 (ko) 반도체 집적 회로
JP3352080B2 (ja) 波形発生装置
JP2957493B2 (ja) Ｐｗｍパルス発生回路
JP2965049B2 (ja) タイミング発生装置
JPH01273128A (ja) Ｃｍｏｓパラレルーシリアル乗算回路、及びその乗算加算ステージ
JP2909218B2 (ja) 半導体試験装置用周期発生器
JP3501923B2 (ja) 半導体試験装置用タイミング発生器
JPS59191657A (ja) デジタル・パタ−ン発生器
JP3326890B2 (ja) パルス幅変調回路
JPH03113523A (ja) ラッチ装置
JPH06273489A (ja) デジタル・パターン発生器
JPH0555832A (ja) デジタル信号発生器
KR19990068979A (ko) 클락 신호 발생기
JPH0766041B2 (ja) 論理波形生成器
JP2001013222A (ja) 波形生成回路
JPH0651026A (ja) 高速パターンアドレス発生器
JPS5916186A (ja) 記憶装置
JPS6132759B2 (enExample)
JPS60246118A (ja) クロツク発生回路

Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20040309

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040407

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040428

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20040514

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20040608

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20040705

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080709

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080709

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090709

Year of fee payment: 5

LAPS Cancellation because of no payment of annual fees