JPS6132759B2 - - Google Patents
Info
- Publication number
- JPS6132759B2 JPS6132759B2 JP55170376A JP17037680A JPS6132759B2 JP S6132759 B2 JPS6132759 B2 JP S6132759B2 JP 55170376 A JP55170376 A JP 55170376A JP 17037680 A JP17037680 A JP 17037680A JP S6132759 B2 JPS6132759 B2 JP S6132759B2
- Authority
- JP
- Japan
- Prior art keywords
- test
- clock
- ram
- memory
- pseudo
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Tests Of Electronic Circuits (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55170376A JPS5794997A (en) | 1980-12-03 | 1980-12-03 | Memory test system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55170376A JPS5794997A (en) | 1980-12-03 | 1980-12-03 | Memory test system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5794997A JPS5794997A (en) | 1982-06-12 |
| JPS6132759B2 true JPS6132759B2 (enExample) | 1986-07-29 |
Family
ID=15903785
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55170376A Granted JPS5794997A (en) | 1980-12-03 | 1980-12-03 | Memory test system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5794997A (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03203548A (ja) * | 1989-12-27 | 1991-09-05 | Mitsubishi Electric Corp | 電動機 |
-
1980
- 1980-12-03 JP JP55170376A patent/JPS5794997A/ja active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03203548A (ja) * | 1989-12-27 | 1991-09-05 | Mitsubishi Electric Corp | 電動機 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5794997A (en) | 1982-06-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4685089A (en) | High speed, low-power nibble mode circuitry for dynamic memory | |
| US4567579A (en) | Dynamic memory with high speed nibble mode | |
| JP3013714B2 (ja) | 半導体記憶装置 | |
| US4685088A (en) | High performance memory system utilizing pipelining techniques | |
| KR100434211B1 (ko) | 2스텝 메모리 장치 커맨드 버퍼 장치 및 방법 및 메모리장치 및 이를 사용한 컴퓨터 시스템 | |
| JPS618796A (ja) | ダイナミツクメモリ | |
| GB2128830A (en) | Semiconductor memory device | |
| US5440511A (en) | Semiconductor memory device | |
| JPS61500513A (ja) | グリッチ・ロックアウト回路を有するメモリ装置 | |
| US20020131313A1 (en) | High frequency range four bit prefetch output data path | |
| KR960042730A (ko) | 반도체기억장치 | |
| JPS61122996A (ja) | 半導体ダイナミツクメモリデバイス | |
| JPH0447396B2 (enExample) | ||
| JPH10172283A (ja) | 半導体記憶装置及びシステム | |
| JPS6132759B2 (enExample) | ||
| KR920702574A (ko) | 반도체 집적회로 | |
| KR100211483B1 (ko) | 블록 기록 시스템을 이용하는 반도체 메모리 | |
| JP2976276B2 (ja) | タイミング発生器 | |
| KR100219491B1 (ko) | 자동 프리차지 뱅크 선택 회로 | |
| JP2970088B2 (ja) | Lsiテスタ | |
| JP3190781B2 (ja) | 半導体メモリ | |
| JPH06109812A (ja) | タイミング発生装置 | |
| US5542063A (en) | Digital data processing system with facility for changing individual bits | |
| JP2818563B2 (ja) | 同期式メモリ | |
| JPH01202021A (ja) | 書き込みタイミング信号発生回路 |