JP3461829B2 - 緩衝層を有する電力半導体素子 - Google Patents

緩衝層を有する電力半導体素子

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Publication number
JP3461829B2
JP3461829B2 JP52480294A JP52480294A JP3461829B2 JP 3461829 B2 JP3461829 B2 JP 3461829B2 JP 52480294 A JP52480294 A JP 52480294A JP 52480294 A JP52480294 A JP 52480294A JP 3461829 B2 JP3461829 B2 JP 3461829B2
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Japan
Prior art keywords
buffer layer
semiconductor device
power semiconductor
layer
ceramic substrate
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Expired - Lifetime
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JP52480294A
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JPH08509844A (ja
Inventor
ヘルベルト シュヴァルツバウアー，
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Siemens AG
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Siemens AG
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H05K3/0061—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8384—Sintering
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01—ELECTRIC ELEMENTS
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0355—Metal foils

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Ceramic Products (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Description

【発明の詳細な説明】 半導体チップが、圧力焼結された銀粉層を介してセラ
ミック基板と結合されている電力半導体素子は、例え
ば、公開番号0242626B1を有するヨーロッパ特許出願明
細書又はドイツ特許公開（DE）第3414065A1号明細書か
ら公知である。
例えば、銀粉層が使用されるような低温接合技術は、
電力半導体素子の際に、セラミック基板を金属底板と接
合するためにも使用することができる。しかしこの場合
はまさに、導出すべき電力損失により変化する温度は、
かなり異なる熱膨張係数の故に、早期の物質疲労及び亀
裂形成をもたらす。低温度接合技術で通常使用される
層、例えば、焼結された銀粉層は、例えば、鉛−錫をベ
ースとする軟ろうを用いての接合に比べて、確かに著し
く高い熱伝導率を有するが、この得られた接合は、軟ろ
うとは異なり、塑性変形しえないからである。
公開番号0139205を有するヨーロッパ特許出願明細書
から、部分層からなる、例えば、アルミニウム又は銅か
らなる接合層を備えることによる絶縁層と金属基板間の
熱膨張調節が公知であり、その際、これらの部分層に加
えて、例えば、酸化アルミニウム又はその他の酸化物が
付加されている。しかし、この場合の欠点は、高まる電
気抵抗率及び高まる技術費用である。
さて、本発明の課題は、セラミック基板と金属底板間
の高い熱伝導率という利点が保証されたままで、早期の
物質疲労及び亀裂形成という欠点が回避される電力半導
体素子を提供することである。
この課題は、本発明により、請求項１に記載の特徴に
より解決される。
請求項２及び３は、本発明の有利な態様に関する。
本発明を、次に、図に基づいて詳述する。
図は、本発明の電力半導体素子の側面図を示してい
る。この際、本発明の電力半導体素子は、順に、半導体
チップ（CHIP）、接合層１、導体路LB、セラミック基板
SUB、接合層２、低い降伏点を有する材料からなる緩衝
層、もう１つの接合層３及び金属底板BPからなる。
半導体チップCHIPは、典型的に、ドープされたシリコ
ンからなり、かつ例えば銅からなる導体路LBは、典型的
に、例えば酸化アルミニウムからなるセラミック基板SU
B上に施与されており、その際、これはここでは、一般
的に市販されている、いわゆるDCB−基板（直接銅接続
基板）である。底板BPは、例えば銅からなる。接合層２
及び３及び通常、接合層１は、焼結された銀粉からなる
のが有利であり、かつその層厚は、約10μｍである。緩
衝層は典型的に、約20N/mm2の低い降伏点を有し、典型
的に、99％を上回るAl−含分を有する充分に純粋なアル
ミニウムからなり、その際、緩衝層の層厚は、約50〜20
0μｍである。
緩衝層のための材料としては、アルミニウムと並ん
で、低い降伏点及び高い熱伝導率を有するその他の金
属、例えば銅又は銀も使用することができる。
セラミック基板SUB、接合層２及び３及び底板BPから
なる接合の剪断強さは非常に高く、緩衝層DPを設置しな
いと、かなり異なる熱膨張係数の故に、殊に、セラミッ
ク基板SUBと底板BPとの間で、温度変化の際に、機械的
応力が生じる。緩衝層を伴わない場合には、熱機械的応
力により、特に、接合層２及び３中に、早期の物質疲労
減少及び亀裂形成が生ずる。
例えば、軟質純アルミニウムからなる緩衝層（応力緩
衝層）の使用により、この応力が解消し、前記の欠点は
これにより回避されるにもかかわらず、非常に良好な耐
熱性が保証される。
フロントページの続き (56)参考文献 特開 平１−255231（ＪＰ，Ａ) 特開 平４−192341（ＪＰ，Ａ) 特開 平４−363052（ＪＰ，Ａ) 特開 平５−29362（ＪＰ，Ａ) 特開 昭57−132333（ＪＰ，Ａ) 特開 昭60−177634（ＪＰ，Ａ) 特開 昭62−81047（ＪＰ，Ａ) 特開 昭62−254439（ＪＰ，Ａ) 特開 昭63−186434（ＪＰ，Ａ) 実開 昭56−46255（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/12 H01L 21/52 H01L 23/36

Claims (2)

    (57)【特許請求の範囲】
  1. 【請求項１】電力半導体素子において、 セラミック基板（SUB）の一方の面上に、第１の接合層
    （１）により少なくとも１個の半導体チップ（CHIP）と
    機械的に接合された導体路（LB）が施与されており、 セラミック基板の他方の面上に、銅、銀又は99％を上回
    るアルミニウム含分を有する純アルミニウムの群からの
    金属からなる膨張緩衝層（DP）が、第２の接合層により
    施与されており、かつこの緩衝層は、第３の接合層を介
    して金属底板と結合されており、かつ接合層（１、２、
    ３）は、焼結された銀粉からなることを特徴とする、電
    力半導体素子。
  2. 【請求項２】膨張緩衝層（DP）が、50〜200μｍの厚さ
    を有する、請求項１に記載の電力半導体素子。
JP52480294A 1993-05-07 1994-05-02 緩衝層を有する電力半導体素子 Expired - Lifetime JP3461829B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE4315272A DE4315272A1 (de) 1993-05-07 1993-05-07 Leistungshalbleiterbauelement mit Pufferschicht
DE4315272.4 1993-05-07
PCT/DE1994/000483 WO1994027319A1 (de) 1993-05-07 1994-05-02 Leistungshalbleiterbauelement mit pufferschicht

Publications (2)

Publication Number Publication Date
JPH08509844A JPH08509844A (ja) 1996-10-15
JP3461829B2 true JP3461829B2 (ja) 2003-10-27

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Country Status (5)

Country Link
US (1) US5654586A (ja)
EP (1) EP0698290B1 (ja)
JP (1) JP3461829B2 (ja)
DE (2) DE4315272A1 (ja)
WO (1) WO1994027319A1 (ja)

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JPH08509844A (ja) 1996-10-15
DE4315272A1 (de) 1994-11-10
WO1994027319A1 (de) 1994-11-24
EP0698290A1 (de) 1996-02-28
DE59407885D1 (de) 1999-04-08
US5654586A (en) 1997-08-05
EP0698290B1 (de) 1999-03-03

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