JPS58169942A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS58169942A
JPS58169942A JP57050734A JP5073482A JPS58169942A JP S58169942 A JPS58169942 A JP S58169942A JP 57050734 A JP57050734 A JP 57050734A JP 5073482 A JP5073482 A JP 5073482A JP S58169942 A JPS58169942 A JP S58169942A
Authority
JP
Japan
Prior art keywords
alloy
layer
metal piece
package
gold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57050734A
Other languages
English (en)
Inventor
Susumu Kida
貴田　進
Isato Usami
宇佐美　勇人
Eiji Aoki
英二 青木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP57050734A priority Critical patent/JPS58169942A/ja
Priority to EP83301536A priority patent/EP0090566B1/en
Priority to DE8383301536T priority patent/DE3379090D1/de
Priority to US06/477,934 priority patent/US4558346A/en
Priority to IE707/83A priority patent/IE54534B1/en
Publication of JPS58169942A publication Critical patent/JPS58169942A/ja
Pending legal-status Critical Current

Links

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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S228/00—Metal fusion bonding
    • Y10S228/904—Wire bonding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 ｉｌ１発明の技術分野 本発明は半導体チップの裏面と外リードとの（１） 接続の信頼性を向上した半導体装置に関する。
（２）技術の背景 築槓回路パンケージ（以下ＩＣパッケージと略称する）
においマ、半導体チップの裏側からアースをとることが
行われる。第１図にサーディツプ型ＩＣパッケージの概
略断面図が示され、同図において、ｌはパッケージ基体
、２はパッケージ基体の凹所（キャビティ）に取付けら
れた半導体チップ、３は半導体チップと外部配線との接
続用のリード、　４、４′は半導体チップ２−１−の電
極パッドとり一ド３との接続のためのワイヤ、５はキャ
ップ（蓋）、７は半導体チップが溶着される＾、＃膜メ
タライズ層、８はキャンプと基体とを封止する低融点ガ
ラスをそれぞれ示す。
かかるＩＣパッケージにおいて、半導体チップ２に対し
て接地（グランド）をとる場合、金属片６を用いる。金
属片６は、ジャンバチ・７プともターミナルチップとも
呼称される。かかる金属片６を用いる理由は、半導体チ
ップ２をセラミック製のパンケージ基体ｌ上の４０１２
９４１１ｍ　７に接着（２） するには、４００〜４５０℃程度に加熱された基体ｌの
十に半導体チップ２をおき、それをＡｕメタライズ、１
−７とすり合せ、半導体チップ２のシリコンｌ＾Ｕメタ
ライズ層７との合金反応により低融点の合金を形成させ
、固着させるのであるが、この４０１７９４１層７には
、配線に用いられるアルミニウム線を接着すると、封１
時の高温度（４（１０〜５００℃）により　Ａｌと＾Ｕ
が合金反応を起し、接着強度が劣化するため使用できな
いからである。か＜　Ｌ。
て、キャビティ内のＡｕメタライズ；−７１−に金属ハ
ロを接着し、金属片６からアルミニウム線４′で図示の
如く接続をとる。なお金属片６も、半導体チップと同様
にしてパッケージ基体を加熱し、金属片６を４０１７９
４１層７にすり合せその表面の＾ｕ−Ｇｅ合金層を熔融
させ接着される。
金属片６は第２図の断面図に示される構成のもので、例
えばコバール９（鉄・ニッケル　Ｆｅ−Ｎｉ−Ｃｏ合金
）または４２７０イ（Ｆｅ−Ｎｉ合金）等を基体とし、
その一方の表面上にはアルミニウム・シリコン合金（＾
ｌ　−３ｉ　）のクラッドｊｌｆｌＯを、ま（３） た他方の表面−Ｌには金・ゲルマニウム合金（＾Ｕ−Ｇ
ｅ）のクラッド層１１を形成しである。かかる金属片６
は、例えば板状のコバールの一方表面上にＡｌ−５ｉ材
を、また他方表面−トには＾ｕ−Ｇｅ材を配置し、これ
らを圧着圧延して形成される（クラッド法）。
（３）従来技術と問題点 図示のパ・７ケージは、キャンプ５を、４００〜５００
℃の炉内に例えば５分間程度入れて封止すること、すな
わちこの加熱によって低融点ガラス層８を溶融し、それ
の冷却固着によってキャンプ５と基体ｌとを一体化する
ことによって完成する。
このとき、半導体チップ２のシリコン（Ｓｉ）成分が、
前記した熱処理の結果Ａｕ−Ｇｅ合金クラッド層１１内
に入り込み、Ａｕ−Ｇｅ合金がＡｕ−Ｇｅ−３ｉ合金化
し、金属片６の基体１に対する接着力が著しく低下する
ことが確認された。このことはＩＣパンケージの信頼性
を損なうことになり出火な問題である。
（４）発明の目的 本発明は上記従来の欠点に鑑み、ＩＣパンケー（４） ジ内に形成されたＡｕメタライズ層と外リートを接続す
る際に使用される金属片（ターミナルチップ）のパンケ
ージ基体に対する接着力が前記１ｃパンケージの熱処理
によって半導体チップからシリコン成分が浸出しても、
低下することのない信頼性の為い半導体装置を提供する
ことを目的とする。
（５）発明の構成 そしてこの目的は本発明によれば、導電性金属片を基体
とし、その一方の面にアルミニウムシリコン合金層が形
成され、他方の面に金−シリコン合金層が形成された金
属片を介し′（半導体簗積回路チップが固着された金メ
タライスＩ−との電気的接続をとる如き金属片を提供す
ることによ−７て達成され、かかる導電性金属片は鉄−
二・ノケルーコバルト合金、鉄−ニッケル合金またはニ
ッケルで形成し、その他方の面に形成する金属層は金−
シリコン−ゲルマニウム合金の金属層とする。
（６）発明の実施例 以下本発明の一実施例を図面によっ゛（詳述する。
（５） 本願の発明者は、前記した従来技術による金属片６とパ
ッケージ基体ｌとの接着力低下が、封止熱処理において
半導体チップのシリコン成分が、金属片６のＡｕ−Ｇｅ
合金クラッド層１１に入り込み、＾ｕ−Ｇｅ合金がＡｕ
−Ｇｅ−５ｉ合金化することによることをつきとめ、か
かるシリコン成分の浸入の影響を受けることのない合金
について実験した結果、クラッド層１１を金・シリコン
（Ａｕ−５ｉ　）合金で形成すればよいことを確認した
。
かくして、再び第２図を参照すると、本発明におい“ζ
は、金属片６のパンケージ基体ｌに接着するクラッド層
１１は、従来の＾ｕ−Ｇｅ合金に代えて＾ｕ−５ｉ合金
で形成したものである。金に含まれるべきシリコンの量
は、金とシリコンとの共晶合金の融点が２７０℃である
ことから、金に対して１〜３％程度にした。
かかるＡｕ−５ｉ合金のクラッド層を用いたところ、前
記したＩｃパンケージの封止熱処理の後においても、Ａ
ｕ−５ｉクラツド層とセラミックのパンケージ基体との
間の接着力の低下は認められながっ（６） た。また、＾ｕ−５ｉ合金タラらド層を形成するための
コストは、従来の場合とほぼ同じであることも確認され
た。
従来例において、Ａｕ−Ｇｅ合金が金属片６の基体】へ
の接着後においてＡｕ−Ｇｅ−３ｉ合金化することによ
り、金属片６の基体１に対する接着力が低）したのであ
るが、クラッド層１１を最初からＡｕ−Ｇｅ−５ｉ合金
で形成しておくと、金属片６の基体への接着後において
は、封止熱処理の悪影響が発生しないことも確認された
。かくして、本発明の実施例においては、クラッド層を
始めからへυ−Ｇｔ３Ｓｉ合金で形成するもので、Ｇｅ
、　Ｓｔの組成は例えば以下の範囲とするのが好ましい
−Ｇｅ：１２〜Ｏ％、Ｓ：：０．３〜３％、残りを＾Ｕ
とする。
本発明にかかる金属片は従来とｌｉｌ様クラり）法で形
成され、またそれのパッケージ基体への接着も従来技術
の場合と全く同様になされる。すなわち、４００〜４５
０℃程度に加熱された基体の金ペーストのメタライズ層
に金属片のＡｕ−５ｉ層をすり合せ接着させる。Ａｌ１
−５ｉ　　（Ｓｉ　：　０〜０．５％）り（７） フッド層ＩＯは従来どおりであり、アルミニウム線４′
のボンディング（接着）は従来と全く同様になされる。
（７）発明の効果 以上、詳細に説明したように、本発明の半導体装置にお
いては、へ〇メタライズ層との接続をとるための金属片
（ターミナルチップ）をＩＣパッケージの基体に接着し
た後、当該パッケージが封止のための熱処理を受けても
、その影響を受けることがなく、パッケージに対する接
着力を維持するので、ＩＣパッケージの信頼性保持に効
果大である。
【図面の簡単な説明】
第１図は半導体築槓回路パッケージのキャンプは取付け
てない状態での概略断面図、第２図は第１図のパッケー
ジ番ご用いる接続用端子の断面図である。 １−パッケージ基体、２−半導体チツブ−３−リード、
　４．４　’−ワイヤ、５−キャンプ、６−金属片（タ
ーミナルチップ）、７−＾Ｕメタライズ層、８＝−低融
点ガラス、（８） ９−コバール、１（１−ＡＲ−５ｉ合金クラッド層、１
１−−−＾ｕ−Ｇｅ　、＾ｕ−ＳｔまたはＡｕ−Ｇｅ−
５ｉ合金のクラッド層 特　許　出願人　　富士通株式会社 代理人　弁理士　　松　岡　宏四部　・”、１　。 °１Ｌ ’ｅ？に＝！−Ｊ− （９） 第１ｒｓ！Ｉ 手続補正書（１１発） 特許庁長官殿 １、ｌｉｆ’ｌのノ、！２ノ； 昭和タフｒ１持訂屓１第夕ｔ）７３呼工Ｊ２イと明の名
（ｊ、半導体装置 ３　補１１を４６と ・ｌｉ　ｌ’ｌとＪ）関ｆ１　　　　　　特許出願人ｆ
１１１！１　　神≦（用県用崎市中１叫４　ｌｌＮ１１
中１０１５番地（５２２）名ｆう・富士通株式会社 ４　代　　理　　　人　　　　　イ１所　神全用県用ｔ
ｈ酌ＩＩ中ハ；Ｉ区Ｉ１１・１１川１０１５番地８補１
１の内８別紙の通り １）本願明細書第１１７Ｉ第５行乃至第１７行の特許請
求の範囲を以下の様に補正する。 （２）前記導電性金属片は鉄−ニッケルーコバルト合金
または鉄−ニッケル合金またはニッケルであることを特
徴とする特鈴錆求の範囲第１Ｊｊ４ｄｄ載の半導体装置
。 （３）前記金−シリコン系合金が金−シリコ／−ゲルマ
ニウム合金であることを特徴とする請求の範囲４１項記
載の半導体装置。」 ２）本願明細書第５］ｉ［第８行乃至１１１７行を以下
の様に補正する。 ［上記の目的は、パッケージ基体κ形成ざれた表メメフ
イズ層に半導体チップと導′ｄ性の金属片とが固着され
、且つ該金属片上にワイヤボ／ディ／グが成された半導
体装置であって、該金属片は該金メタライズ層と対向す
る面に金Ｏシリコ／系合金層を、該ワイヤポ／ディ／グ
が成される面にアルミニツム又はアルミ−ラム０フリコ
フ合金層をそれぞれ有することｔ−特徴とする半導体装
置によ−．）Ｃ４成される。」

Claims (1)

  1. 【特許請求の範囲】 （１１導電性金属片を基体とし、その−力の面にアルミ
    ニウムーシリコン合金層が形成され、他方の而に金−シ
    リコン合金層が形成された金属片を介し゛ζ半導体集積
    回路チップが固着された金メタライズ層との電気的接続
    をとる様にしたことを特徴とする半導体装置。 （２）前記導電性金属片は鉄−ニソケルーコハルト合金
    または鉄−ニソケル合金またはニッケルであることを特
    徴とする特許請求の範囲第１項記載の半導体装置。 （３）前記金属片の他方の面に形成される金属ｌ−が金
    −シリコン−ゲルマニウム合金であることを特徴とする
    特許請求の範囲第１項記載の半導体装置。
JP57050734A 1982-03-29 1982-03-29 半導体装置 Pending JPS58169942A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP57050734A JPS58169942A (ja) 1982-03-29 1982-03-29 半導体装置
EP83301536A EP0090566B1 (en) 1982-03-29 1983-03-18 Semiconductor device package
DE8383301536T DE3379090D1 (en) 1982-03-29 1983-03-18 Semiconductor device package
US06/477,934 US4558346A (en) 1982-03-29 1983-03-23 Highly reliable hermetically sealed package for a semiconductor device
IE707/83A IE54534B1 (en) 1982-03-29 1983-03-29 Semiconductor device package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57050734A JPS58169942A (ja) 1982-03-29 1982-03-29 半導体装置

Publications (1)

Publication Number Publication Date
JPS58169942A true JPS58169942A (ja) 1983-10-06

Family

ID=12867075

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57050734A Pending JPS58169942A (ja) 1982-03-29 1982-03-29 半導体装置

Country Status (5)

Country Link
US (1) US4558346A (ja)
EP (1) EP0090566B1 (ja)
JP (1) JPS58169942A (ja)
DE (1) DE3379090D1 (ja)
IE (1) IE54534B1 (ja)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4570337A (en) * 1982-04-19 1986-02-18 Olin Corporation Method of assembling a chip carrier
EP0139029A1 (en) * 1983-10-19 1985-05-02 Olin Corporation Improved semiconductor package
US4837928A (en) * 1986-10-17 1989-06-13 Cominco Ltd. Method of producing a jumper chip for semiconductor devices
JPH06244231A (ja) * 1993-02-01 1994-09-02 Motorola Inc 気密半導体デバイスおよびその製造方法
JP2938344B2 (ja) * 1994-05-15 1999-08-23 株式会社東芝 半導体装置
US5508556A (en) * 1994-09-02 1996-04-16 Motorola, Inc. Leaded semiconductor device having accessible power supply pad terminals
JPH11305205A (ja) * 1998-04-22 1999-11-05 Hitachi Ltd 液晶表示装置
US6062461A (en) * 1998-06-03 2000-05-16 Delphi Technologies, Inc. Process for bonding micromachined wafers using solder
US6564449B1 (en) * 2000-11-07 2003-05-20 Advanced Semiconductor Engineering, Inc. Method of making wire connection in semiconductor device
KR100706516B1 (ko) 2001-02-06 2007-04-11 앰코 테크놀로지 코리아 주식회사 반도체 패키지
US20130167482A1 (en) * 2011-09-08 2013-07-04 Advanced Numicro Systems, Inc. Vacuum sealing process of a mems package
US10014189B2 (en) * 2015-06-02 2018-07-03 Ngk Spark Plug Co., Ltd. Ceramic package with brazing material near seal member

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5128461A (ja) * 1974-09-03 1976-03-10 Nippon Electric Co
JPS5527615A (en) * 1978-08-17 1980-02-27 Sumitomo Metal Mining Co Ltd Clad material for ic package
JPS5758340A (en) * 1980-09-24 1982-04-08 Nec Corp Semiconductor device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3497774A (en) * 1967-06-07 1970-02-24 Beckman Instruments Inc Electrical circuit module and method of manufacture
US3585711A (en) * 1968-09-06 1971-06-22 Us Navy Gold-silicon bonding process
JPS598358Y2 (ja) * 1978-02-08 1984-03-15 京セラ株式会社 半導体素子パツケ−ジ
JPS55153341A (en) * 1979-05-17 1980-11-29 Toshiba Corp Semiconductor device
JPS56105660A (en) * 1980-01-28 1981-08-22 Nec Corp Semiconductor device
EP0039507A1 (en) * 1980-05-05 1981-11-11 LeaRonal, Inc. A process of packaging a semiconductor and a packaging structure for containing semiconductive elements
JPS5854644A (ja) * 1981-09-28 1983-03-31 Nec Corp ボンデイング用樹脂基板
US4447857A (en) * 1981-12-09 1984-05-08 International Business Machines Corporation Substrate with multiple type connections

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5128461A (ja) * 1974-09-03 1976-03-10 Nippon Electric Co
JPS5527615A (en) * 1978-08-17 1980-02-27 Sumitomo Metal Mining Co Ltd Clad material for ic package
JPS5758340A (en) * 1980-09-24 1982-04-08 Nec Corp Semiconductor device

Also Published As

Publication number Publication date
IE830707L (en) 1983-09-29
IE54534B1 (en) 1989-11-08
EP0090566B1 (en) 1989-01-25
US4558346A (en) 1985-12-10
DE3379090D1 (en) 1989-03-02
EP0090566A2 (en) 1983-10-05
EP0090566A3 (en) 1985-10-30

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