1287277 A7 --------- -B7 五、發明説明（1 ) 粗.闞申請案的交互I考 本案係為共同審查中且以引用方式整體併入本文之 2000年4月13曰的專利申請案〇9/548,946之部份接續申請 案。 t明背景 1·發明簸齊 本發明有關於諸如功率MOSFET元件等半導體功率切 換元件，更特別有關於一種包括模製無線暴露汲極封裝體 之半導體元件，以及用於封裝該封裝體之方法。 L習知技藝描沭 半導體功率切換元件、特別是功率MOSFET元件正不 斷拓展先進電阻的下限，雖然矽技術在過去十年已有鉅大 進展，但仍採用幾十年來大致相同的封裝技術作為主要的 封裝方式，伴隨銘或金線互連組件進行的環氧樹脂或焊料 晶粒附接仍然係為較佳的功率元件封裝方法。近來已藉由 在封裝體内直接經由一低電阻焊料接點將晶粒連接至導線 來製造封裝體。利用一第二導線架元件及焊料來連接封裝 導體與第一導線架’能夠產生直接連接。並且，可定製第 二導線架的尺寸與形狀藉以配合晶片元件並盡量降低電阻 與熱阻。 當在一晶片内的一閘極接點完成金打線接合時，使用 黏劑可能造成難以控制的樹脂滲流並會干擾到閘極接合的 接觸完整性。當在源極和汲極接點使用充填有銀的黏劑 時，因為黏劑不會選擇性流動，所產生的元件一般在間極 S4糸紙張尺度適用中國國家標準M規格（2】〇X297公釐） 1287277 A7 ^—----!Z_ 五、"~~ 或及極内較容易有源極短路。此外，黏劑一般具有不如焊 料之導電性。 近來已使用銅帶將晶粒耦合至導線，一般而言，此等 配置中’超過60%的晶粒區域係由銅帶及銅帶底下的黏劑 所佔據’這代表只有較少模製塑膠可供穩固地固持住内部 組裝件，因為對於黏劑分配較大區域，亦代表晶片元件有 更大機會形成空隙。 最後’對於半導體元件封裝之另一問題係為消除元件 所發出的熱量，一般而言，功率]^081^£丁元件可產生很大 的熱量。 發明概述 本發明係提供一種包括有一導線架及耦合至該導線架 的一晶粒之半導體元件。導線架係包括一源極墊及一閘極 墊、及從源極墊延伸的複數個導線及從閘極墊延伸的至少 一導線。半導體元件進一步包括一汲極墊及一體部，汲極 區耦合至晶粒的一汲極區，而體部中界定有一窗口。體部 大致包套住導線架及晶粒，使得與晶粒相對之汲極墊的一 表面暴露通過窗口。 根據本發明的一型態，沒極塾以軟焊材料輕合至晶粒。 根據本發明的另一型態，没極塾包括一側唇，且半導 體元件進一步包括一導線執，導線執包括複數個導線，導 線執在側唇上搞合至没極塾。 根據本發明另一型態，沒極墊以軟焊材料輕合至晶 粒，且導線軌以軟焊材料耦合至側唇。 gs%紙張尺度適用中國國家標準（®S) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁)1287277 A7 --------- -B7 V. INSTRUCTIONS (1) The interaction of the rough and 阚 application I is based on the same review and is incorporated by reference in this article on April 13, 2000. Part of the patent application 〇 9/548,946 continues the application. BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to semiconductor power switching components such as power MOSFET components, and more particularly to a semiconductor component including a molded wireless exposed drain package, and a method for packaging the package. L-Knowledge Techniques describe semiconductor power switching components, especially power MOSFET components, which are expanding the lower limit of advanced resistors. Although 矽 technology has made great progress in the past decade, it still uses the same packaging technology as the main one for decades. The packaging method, epoxy or solder die attach with the inscription or gold wire interconnect assembly is still a preferred power component packaging method. Packages have recently been fabricated by attaching die to a wire directly through a low resistance solder joint within the package. The use of a second leadframe component and solder to connect the package conductor to the first leadframe' can create a direct connection. Also, the size and shape of the second leadframe can be customized to match the wafer components and minimize resistance and thermal resistance. When a gold bond is completed at a gate contact in a wafer, the use of an adhesive may cause uncontrolled resin permeation and may interfere with the contact integrity of the gate bond. When the silver-filled adhesive is used at the source and the drain contact, since the adhesive does not selectively flow, the resulting component is generally applied to the Chinese National Standard M specification at the inter-pole S4糸 paper scale (2)〇X297 PCT) 1287277 A7 ^—----!Z_ Five, "~~ or the inner pole is easier to short circuit. In addition, the adhesive generally has less conductivity than the solder. Recently, copper ribbons have been used to couple the die to the wires. In general, in these configurations, 'more than 60% of the grain area is occupied by the copper tape and the adhesive under the copper tape'. This means that there are only less molded plastics. It is possible to firmly hold the internal assembly because it also represents a greater opportunity for the wafer component to form a void for a larger area of adhesive distribution. Finally, another problem with semiconductor component packaging is to eliminate the heat emitted by the component. In general, the power of the device can generate a large amount of heat. SUMMARY OF THE INVENTION The present invention provides a semiconductor component including a leadframe and a die coupled to the leadframe. The lead frame includes a source pad and a pad, and a plurality of wires extending from the source pad and at least one wire extending from the pad pad. The semiconductor component further includes a drain pad and an integral portion, the drain region being coupled to a drain region of the die and a window defined in the body. The body substantially encases the leadframe and the die such that a surface of the pad opposite the die is exposed through the window. According to one form of the invention, the solder is not bonded to the die. According to another aspect of the invention, the side lip is not included, and the semiconductor component further includes a wire guide, the wire wire includes a plurality of wires, and the wire is held on the side lip to be inconsistency. According to another aspect of the invention, the electrode pad is lightly bonded to the crystal with a solder material and the wire rail is coupled to the side lip with a solder material. The gs% paper scale applies to the Chinese National Standard (®S) A4 specification (210X297 mm) (please read the notes on the back and fill out this page)
1287277 A7 B7 五、發明説明（3 ) 根據本發明另一型態，導線架進一步包括位於導線架 各端之兩個束桿。 (請先閲讀背面之注意事項再填寫本頁) 本發明亦提供一種用於封裝半導體晶粒之方法，其中 此方法包括提供一導線架及將一晶粒耦合至導線架，此導 線架包括一源極墊及一閘極墊。一汲極墊係耦合至晶粒的 一汲極區，且一體部放置在導線架及晶粒周圍，此體部中 界定有一窗口，使得與晶粒相對的汲極墊表面係暴露通過 窗口且導線架的導線延伸通過體部。 因此，本發明提供一種改良的晶片元件及該晶片元件 之製造方法，因為焊料回流期間汲極接點直接位於汲極墊 上且源極及閘極凸塊則直接耦合至導線架，所以此程序不 需要任何打線接合，所產生的閘極接點比閘極打線接合程 序所產生者更加可靠。此外，對於源極及汲極接點皆使用 焊料，因為兩接點均與不可濕潤區域相隔離，所以只在可 焊性金屬上發生濕潤而閘極較不易短路。此外，焊料合金 具有比黏劑更好的傳導性，導致晶片元件具有較低的 RD Son性能0 最後，因為汲極墊暴露通過體部，晶片元件已改善散 熱。 可參照圖式並藉由下文中較佳示範性實施例的詳細描 述而得知本發明的其他特性及優點，其中類似的編號代表 類似的元件。 圖式簡單說明 第1圖為根據本發明之一半導體元件的俯視立體圖；1287277 A7 B7 V. INSTRUCTION DESCRIPTION (3) According to another aspect of the invention, the lead frame further includes two beam bars at each end of the lead frame. (Please read the note on the back and then fill out this page.) The present invention also provides a method for packaging a semiconductor die, wherein the method includes providing a leadframe and coupling a die to the leadframe, the leadframe including a Source pad and a pad pad. An anode pad is coupled to a drain region of the die, and the integral portion is placed around the lead frame and the die, and a window is defined in the body such that the surface of the pad opposite the die is exposed through the window and The wires of the lead frame extend through the body. Accordingly, the present invention provides an improved wafer component and a method of fabricating the same, wherein the gate is directly on the drain pad and the source and gate bumps are directly coupled to the leadframe during solder reflow, so the program does not Any wire bonding is required and the resulting gate contacts are more reliable than those produced by the gate wire bonding process. In addition, solder is used for both the source and the drain contacts. Since both contacts are isolated from the non-wettable region, only the solderable metal is wet and the gate is less susceptible to short-circuit. In addition, the solder alloy has better conductivity than the adhesive, resulting in a lower RD Son performance of the wafer component. Finally, the wafer component has improved heat dissipation because the drain pad is exposed through the body. Other features and advantages of the present invention will become apparent from the Detailed Description of the Drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a top perspective view of a semiconductor device in accordance with the present invention;
Si本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） 1287277 A7 I-------!Z______ 五、發明説明（4 ) 第2圖為第1圖所示之半導體元件的仰視立體圖； 第3圖為第1圖所示之半導體元件的分解圖； 第4圖為根據本發明一項替代性實施例之一半導體元 件的侧剖視圖，其中已移除體部； 第5圖為根據本發明供一半導體元件使用之一模製體 部或封裝體的仰視立體圖； 第6圖為根據本發明供一半導體元件使用的一凸塊化 晶粒之部份侧剖視圖； 第7圖為根據本發明之一晶粒與一導線架之間的一焊 料凸塊的放大圖。 疫定示IL性實施例的描诚 第1圖顯示一半導體元件10，半導體元件10包括一體部 或封裝體11及複數個導線12，導線12係包括源極導線128、 汲極導線12d及延伸的一閘極導線12g。體部較佳係為模製 二件式封裝體，如第2及5圖所示，體部中界定有一窗口13， 體部較佳包含熱固性聚合物。 參照第3圖，提供一導線架20,導線架包括一源極墊21 及一閘極墊22，亦提供一晶粒23以耦合至導線架。 根據本發明之一封裝配置係可特別有效用於功率 MOSFET元件t，因此，晶粒較佳為一功率晶粒。 I 並且θθ粒較佳係為此技藝常稱為“凸塊化晶粒，，的一件式 物品。如第6圖所示，凸塊化晶粒係包括晶粒3〇、焊料凸塊 31、以及作為焊料凸塊與晶粒的頂表面之間的中間層之下 凸塊材料32。下凸塊材料較佳係為Tiw、Cu、Au或均等物 fc#紙張尺度適用申國國家標準（CNS) A4規格（210X297公釐） '二7一I— ---Si paper size applies to China National Standard (CNS) A4 specification (210X297 mm) 1287277 A7 I-------!Z______ V. Invention description (4) Figure 2 shows the semiconductor component shown in Figure 1. 3 is an exploded view of the semiconductor device shown in FIG. 1; FIG. 4 is a side cross-sectional view of the semiconductor device according to an alternative embodiment of the present invention, in which the body has been removed; A bottom perspective view of a molded body or package for use in a semiconductor device in accordance with the present invention; FIG. 6 is a partial side cross-sectional view of a bumped die for use in a semiconductor device in accordance with the present invention; An enlarged view of a solder bump between a die and a leadframe in accordance with the present invention. DETAILED DESCRIPTION OF THE INVENTION The first embodiment of the present invention shows a semiconductor device 10 comprising an integral portion or package 11 and a plurality of wires 12 including a source wire 128, a drain wire 12d and an extension. One gate wire 12g. Preferably, the body is a molded two-piece package. As shown in Figures 2 and 5, a window 13 is defined in the body, and the body preferably comprises a thermoset polymer. Referring to Figure 3, a leadframe 20 is provided. The leadframe includes a source pad 21 and a gate pad 22, and a die 23 is also provided for coupling to the leadframe. A package configuration in accordance with the present invention is particularly effective for power MOSFET component t, and therefore, the die is preferably a power die. I and θ θ particles are preferably a one-piece article commonly referred to as "bumped grains" for this technique. As shown in Fig. 6, the bumped grain system includes grains 3 〇, solder bumps 31 And as an intermediate layer between the solder bump and the top surface of the die, the bump material 32. The lower bump material is preferably Tiw, Cu, Au or equivalent fc# paper scale applicable to the national standard of the country ( CNS) A4 size (210X297 mm) 'two 7 one I — ---
.訂— (請先閲讀背面之注意事項再填寫本頁) 1287277 A7 B7 五、發明説明（5 ) 之其中一者。第6圖所示的範例中，下凸塊材料分解成三 層：Cu鍍層32a、喷濺Cu 32b及喷濺Ti 32c。 (請先閲讀背面之注意事項再填寫本頁) 凸塊化晶粒較佳覆晶式附接至導線架上，亦即從一鋸 切卷帶（sawn tape)“翻覆，，在導線架上。凸塊化晶粒放置在 導線架上使得閘極焊料凸塊3 1 g接觸導線架上的閘極墊 22，而源極焊料凸塊31s則接觸導線架上的源極墊21。 導線架較佳包含鍍Ni或Ni_Pd的Cu合金，焊料凸塊較 佳包含具有均等融化溫度之95Pb/5Sn或無Pb的焊料。 如第3圖所示，提供一汲極晶片或汲極墊5〇以耦合至晶 粒的背側，汲極墊係提供半導體元件的汲極接點並身為半 導體元件的主要排熱部並且亦作為晶粒背部屏障。較佳， 汲極塾包含鍵Ni或Ni-Pd的Cu合金，沒極墊較佳具有4至6 密耳的厚度，較佳利用使晶粒背部與汲極墊接合在一起的 軟焊材料51將没極墊輕合至晶粒背侧。軟焊材料亦在半導 體元件周圍模製體部期間吸收壓縮應力。軟焊材料較佳係 包含 88PblOSn2Ag 、85PblOSb5Sn 、90Pbl0Sb 及 82.5?1>158112.5八§或無？13焊料，且在較佳的軟焊材料中具有 均等的融化溫度。軟焊材料具有比焊料凸塊更低的融化溫 度’因此可讓軟焊材料回流而不使已先前受到回流的焊料 凸塊產生回流’藉以將晶粒耦合至導線架。並且，如第7 圖所示’晶粒23上的焊料凸塊並未在導線架2〇與晶粒23之 間“崩潰”，軟焊料33亦可放置於焊料凸塊31與導線架之間 以幫助接合焊料凸塊。 如苐3圖所示，導線架包括自由槽52，自由槽有助於避 3’s3本紙張尺度適用中國國家標準（CNS) Α4規格（210X297公釐） 1287277 A7 B7 五、發明説明（6 ) 免模製空隙。 因為汲極墊耦合至晶粒背侧，晶粒背侧較佳包括一背 部金屬，此背部金屬係促進汲極傳導性並有助於作為矽基 材與汲極墊之間唯一的歐姆性接點，背部金屬較佳係包含 具有Au套料的Ti-Ni-Ag背部金屬或均等物。 一旦汲極墊已耦合至晶粒時，體部放置在導線架、晶 粒及汲極墊周圍，藉以保護及完成半導體元件。如第5圖所 示，體部中界定有窗口 13以暴露出汲極墊。 使用完成的半導體元件時，汲極墊作為汲極接點，而 導線則作為源極接點。閘極導線60作為閘極接點。 如第4圖所示，一項替代性實施例中，汲極墊50可包括 一側唇70，導線架則包括一導線執71，導線軌71包括一 v 形溝72。再度利用軟焊材料來將汲極墊耦合至晶粒，但此 替代性實施例中亦可用以將側唇耦合至導線側執。軟焊材 料將侧唇耦合至v形槽中的導線側執，因此，從導線侧執延 伸的導線12d將作為汲極接點，而源極導線12s則將作為源 極接點，一閘極導線亦作為閘極接點。較佳仍提供窗口 13， 其中汲極墊50可作為排熱部。 最後，可包括束桿80藉以提供源極墊的額外機械性支 撐，束桿亦有助於維持源極墊的共面性。 為此，本發明提供一種半導體元件之改良的封裝配 置，其可經由一汲極夾件或汲極墊以將晶粒的汲極區直接 連接至一印刷電路板（PCB)。汲極夾件或汲極墊亦對於半 導體元件作為排熱部，並不需要打線接合，且半導體元件 9 (請先閲讀背面之注意事項再填寫本頁) ΘΜ本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐） 1287277 A7 _B7_ 五、發明説明（7 ) 係具有比起許多目前半導體元件較低之RDSon性能。 雖然已經參照特定示範性實施例來描述本發明，可瞭 解其預定涵蓋申請專利範圍的範疇内之所有修改及均等 物。 元件標號對照 10…半導體元件 31s…源極焊料£ 11…體部或封裝體 32…下凸塊材料 12…導線 32a…Cu鍛層 12d···汲極導線 32b···喷錢Cu 12g，60…閘極導線 32c…喷濺Ti 12s···源極導線 33…軟焊料 13…窗口 50…汲極墊 20…導線架 51…軟焊材料 21…源極墊 52…自由槽 22…閘極墊 70…侧唇 23,30…晶粒 71…導線執 31…焊料凸塊 72…v形溝 31g···閘極焊料凸塊 80…束桿 10 (請先閲讀背面之注意事項再填寫本頁) 龄S本紙張尺度適用中國國家標準（CNS) A4規格（210X297公釐）.Order — (Please read the notes on the back and fill out this page) 1287277 A7 B7 5. One of the invention notes (5). In the example shown in Fig. 6, the lower bump material is decomposed into three layers: a Cu plating layer 32a, a sputtering Cu 32b, and a sputtering Ti 32c. (Please read the note on the back and fill out this page.) The bumped die is preferably flip-chip attached to the lead frame, that is, "overturned from a sawn tape" on the lead frame. The bumped die is placed on the leadframe such that the gate solder bumps 3 1 g contact the gate pads 22 on the leadframe and the source solder bumps 31s contact the source pads 21 on the leadframe. Preferably, the Ni alloy is plated with Ni or Ni_Pd, and the solder bump preferably comprises 95Pb/5Sn or Pb-free solder having a uniform melting temperature. As shown in FIG. 3, a drain wafer or a drain pad is provided. Coupled to the back side of the die, the drain pad provides the drain contact of the semiconductor component and acts as the primary heat sink for the semiconductor component and also acts as a back barrier for the die. Preferably, the drain 塾 contains the bond Ni or Ni- The Pd Cu alloy, the non-polar pad preferably has a thickness of 4 to 6 mils, and is preferably bonded to the back side of the die by a solder material 51 that bonds the back of the die to the drain pad. The solder material also absorbs compressive stress during molding of the body around the semiconductor component. The solder material preferably includes 88P. blOSn2Ag, 85PblOSb5Sn, 90Pbl0Sb and 82.5?1>158112.5 § or no?13 solder, and have equal melting temperatures in the preferred solder material. The solder material has a lower melting temperature than the solder bumps. Reflowing the solder material without reflowing the solder bumps that have been previously reflowed 'by coupling the die to the leadframe. And, as shown in Figure 7, the solder bumps on the die 23 are not in the leadframe 2" and "crash" between the die 23, the soft solder 33 can also be placed between the solder bump 31 and the lead frame to help bond the solder bump. As shown in Figure 3, the lead frame includes a free slot 52, free The trough helps to avoid the 3's3 paper scale applicable to the Chinese National Standard (CNS) Α4 specification (210X297 mm) 1287277 A7 B7 V. Invention Description (6) Mold-free void. Because the bungee pad is coupled to the back side of the die Preferably, the back side of the die includes a back metal which promotes the conductivity of the gate and contributes to being the only ohmic junction between the tantalum substrate and the drain pad. The back metal preferably comprises Au. Nesting Ti-Ni-Ag back metal Equalization. Once the pad is coupled to the die, the body is placed around the leadframe, die and pad to protect and complete the semiconductor component. As shown in Figure 5, a window 13 is defined in the body. To expose the drain pad. When using the completed semiconductor component, the drain pad acts as the drain contact and the wire acts as the source contact. The gate wire 60 acts as the gate contact. As shown in Figure 4, In an alternative embodiment, the pad 50 can include a side lip 70, the lead frame includes a wire holder 71, and the wire track 71 includes a v-shaped groove 72. The solder pad is again used to couple the pad to the crystal. Granules, but this alternative embodiment can also be used to couple the side lips to the side of the wire. The solder material couples the side lip to the side of the wire in the v-groove. Therefore, the wire 12d extending from the wire side will serve as the drain contact, and the source wire 12s will serve as the source contact, a gate. The wire also acts as a gate contact. Preferably, a window 13 is provided, wherein the drain pad 50 can serve as a heat exhausting portion. Finally, the beam 80 can be included to provide additional mechanical support for the source pad, which also helps maintain the coplanarity of the source pad. To this end, the present invention provides an improved package configuration for a semiconductor device that can be connected directly to a printed circuit board (PCB) via a drain clip or a drain pad. The bucker clip or the bungee pad also acts as a heat-dissipating part for the semiconductor component, and does not require wire bonding, and the semiconductor component 9 (please read the note on the back side and then fill in this page). The paper size applies to the Chinese national standard (CNS). A4 size (210X297 mm) 1287277 A7 _B7_ V. Inventive Note (7) has a lower RDSon performance than many current semiconductor components. Although the present invention has been described with reference to the specific exemplary embodiments, it is understood that all modifications and equivalents are intended to be included within the scope of the claims. Element number comparison 10...Semiconductor element 31s...Source solder £11...body or package 32...lower bump material 12...wire 32a...Cu forging layer 12d···dip wire 32b···spraying money 12g, 60...gate wire 32c...sputter Ti 12s··source wire 33...soft solder 13...window 50...thin pad 20... lead frame 51...soft solder material 21...source pad 52...free slot 22...gate Pole pad 70...side lip 23,30...die 71...wire stop 31...solder bump 72...v-shaped groove 31g···gate solder bump 80...beam 10 (please read the back note first and then fill in On this page) Age S paper size applies to China National Standard (CNS) A4 specification (210X297 mm)