JP3303002B2 - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JP3303002B2
JP3303002B2 JP50673892A JP50673892A JP3303002B2 JP 3303002 B2 JP3303002 B2 JP 3303002B2 JP 50673892 A JP50673892 A JP 50673892A JP 50673892 A JP50673892 A JP 50673892A JP 3303002 B2 JP3303002 B2 JP 3303002B2
Authority
JP
Japan
Prior art keywords
circuit
mos transistor
control gate
semiconductor device
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP50673892A
Other languages
English (en)
Japanese (ja)
Other versions
JPWO1992016971A1 (ja
Inventor
直 柴田
忠弘 大見
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Publication of JPWO1992016971A1 publication Critical patent/JPWO1992016971A1/ja
Application granted granted Critical
Publication of JP3303002B2 publication Critical patent/JP3303002B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/5013—Half or full adders, i.e. basic adder cells for one denomination using algebraic addition of the input signals, e.g. Kirchhoff adders
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/49—Computations with a radix, other than binary, 8, 16 or decimal, e.g. ternary, negative or imaginary radices, mixed radix non-linear PCM
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/005—Electric analogue stores, e.g. for storing instantaneous values with non-volatile charge storage, e.g. on floating gate or MNOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4818—Threshold devices
    • G06F2207/482—Threshold devices using capacitive adding networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4818—Threshold devices
    • G06F2207/4826—Threshold devices using transistors having multiple electrodes of the same type, e.g. multi-emitter devices, neuron-MOS devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/54—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using elements simulating biological cells, e.g. neuron
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/561—Multilevel memory cell aspects
    • G11C2211/5611—Multilevel memory cell with more than one control gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Computational Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Health & Medical Sciences (AREA)
  • Biomedical Technology (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biophysics (AREA)
  • Software Systems (AREA)
  • Evolutionary Computation (AREA)
  • Nonlinear Science (AREA)
  • Artificial Intelligence (AREA)
  • Molecular Biology (AREA)
  • Computational Linguistics (AREA)
  • Data Mining & Analysis (AREA)
  • Neurology (AREA)
  • Power Engineering (AREA)
  • General Health & Medical Sciences (AREA)
  • Algebra (AREA)
  • Logic Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
JP50673892A 1991-03-21 1992-03-21 半導体装置 Expired - Fee Related JP3303002B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP3-83152 1991-03-21
JP8315291 1991-03-21
PCT/JP1992/000347 WO1992016971A1 (fr) 1991-03-21 1992-03-21 Dispositif a semi-conducteur

Publications (2)

Publication Number Publication Date
JPWO1992016971A1 JPWO1992016971A1 (ja) 1993-03-04
JP3303002B2 true JP3303002B2 (ja) 2002-07-15

Family

ID=13794263

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50673892A Expired - Fee Related JP3303002B2 (ja) 1991-03-21 1992-03-21 半導体装置

Country Status (6)

Country Link
US (1) US5587668A (cg-RX-API-DMAC7.html)
EP (1) EP0578821B1 (cg-RX-API-DMAC7.html)
JP (1) JP3303002B2 (cg-RX-API-DMAC7.html)
DE (1) DE69229546T2 (cg-RX-API-DMAC7.html)
TW (2) TW208086B (cg-RX-API-DMAC7.html)
WO (1) WO1992016971A1 (cg-RX-API-DMAC7.html)

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5764081A (en) * 1991-05-17 1998-06-09 Theseus Logic, Inc. Null convention interface circuits
CA2103257A1 (en) * 1991-05-17 1992-11-26 Karl M. Fant Null convention speed independent logic
US5656948A (en) * 1991-05-17 1997-08-12 Theseus Research, Inc. Null convention threshold gate
US5664211A (en) * 1993-06-08 1997-09-02 Theseus Research, Inc. Null convention threshold gate
US6020754A (en) * 1991-05-17 2000-02-01 Theseus Logic, Inc. Look up table threshold gates
US5796962A (en) * 1991-05-17 1998-08-18 Theeus Logic Null convention bus
US5930522A (en) * 1992-02-14 1999-07-27 Theseus Research, Inc. Invocation architecture for generally concurrent process resolution
JP3281936B2 (ja) 1992-06-24 2002-05-13 日本電信電話株式会社 論理回路
JPH06250994A (ja) * 1993-02-22 1994-09-09 Sunao Shibata 演算装置
JP3459017B2 (ja) * 1993-02-22 2003-10-20 直 柴田 半導体装置
US5652902A (en) * 1993-06-08 1997-07-29 Theseus Research, Inc. Asynchronous register for null convention logic systems
US5793662A (en) * 1993-06-08 1998-08-11 Theseus Research, Inc. Null convention adder
US5719520A (en) * 1994-02-15 1998-02-17 Tadashi Shibata Multi-valued ROM circuit #7
US6327607B1 (en) 1994-08-26 2001-12-04 Theseus Research, Inc. Invocation architecture for generally concurrent process resolution
KR19990077091A (ko) * 1996-01-25 1999-10-25 피터 토마스 가변 입력 가중치를 가지는 반도체 뉴런
JPH09245110A (ja) * 1996-03-13 1997-09-19 Tadahiro Omi フィードバック回路
ES2117564B1 (es) * 1996-04-24 1999-04-01 Mendez Vigo Barazona Javier Transistor inecuacional o pseudoneuronal.
DE19630111C1 (de) * 1996-07-25 1997-08-14 Siemens Ag Vorrichtungen zur selbstjustierenden Arbeitspunkteinstellung in Verstärkerschaltungen mit Neuron-MOS-Transistoren
JPH10224224A (ja) * 1997-02-03 1998-08-21 Sunao Shibata 半導体演算装置
JPH10283793A (ja) * 1997-02-06 1998-10-23 Sunao Shibata 半導体回路
JPH10224210A (ja) * 1997-02-12 1998-08-21 Fujitsu Ltd 論理回路、フリップフロップ回路及び記憶回路装置
JPH10260817A (ja) 1997-03-15 1998-09-29 Sunao Shibata 半導体演算回路及びデ−タ処理装置
JPH10257352A (ja) 1997-03-15 1998-09-25 Sunao Shibata 半導体演算回路
JPH1196276A (ja) 1997-09-22 1999-04-09 Sunao Shibata 半導体演算回路
US5907693A (en) * 1997-09-24 1999-05-25 Theseus Logic, Inc. Autonomously cycling data processing architecture
US5986466A (en) * 1997-10-08 1999-11-16 Theseus Logic, Inc. Programmable gate array
US6397201B1 (en) 1997-12-02 2002-05-28 David W. Arathorn E-cell (equivalent cell) and the basic circuit modules of e-circuits: e-cell pair totem, the basic memory circuit and association extension
US6031390A (en) * 1997-12-16 2000-02-29 Theseus Logic, Inc. Asynchronous registers with embedded acknowledge collection
JP3811354B2 (ja) * 1997-12-17 2006-08-16 忠弘 大見 演算処理用半導体回路および演算処理方法
US6262593B1 (en) 1998-01-08 2001-07-17 Theseus Logic, Inc. Semi-dynamic and dynamic threshold gates with modified pull-up structures
FI981301A0 (fi) 1998-06-08 1998-06-08 Valtion Teknillinen Prosessivaihtelujen eliminointimenetelmä u-MOSFET-rakenteissa
US6417539B2 (en) * 1998-08-04 2002-07-09 Advanced Micro Devices, Inc. High density memory cell assembly and methods
US6269354B1 (en) 1998-11-30 2001-07-31 David W. Arathorn General purpose recognition e-circuits capable of translation-tolerant recognition, scene segmentation and attention shift, and their application to machine vision
JP4663094B2 (ja) 2000-10-13 2011-03-30 株式会社半導体エネルギー研究所 半導体装置
US7400527B2 (en) * 2006-03-16 2008-07-15 Flashsilicon, Inc. Bit symbol recognition method and structure for multiple bit storage in non-volatile memories
CN103716039B (zh) * 2013-12-04 2016-05-18 浙江大学城市学院 一种基于浮栅mos管的增强型动态全加器
US10461751B2 (en) * 2018-03-08 2019-10-29 Samsung Electronics Co., Ltd. FE-FET-based XNOR cell usable in neuromorphic computing
JP2020052217A (ja) * 2018-09-26 2020-04-02 株式会社ジャパンディスプレイ 表示装置及び電子看板
CN112885830B (zh) * 2019-11-29 2023-05-26 芯恩（青岛）集成电路有限公司 堆叠神经元器件结构及其制作方法
WO2022225948A1 (en) * 2021-04-19 2022-10-27 Trustees Of Dartmouth College Multigate in-pixel source follower

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4950917A (en) 1988-07-27 1990-08-21 Intel Corporation Semiconductor cell for neural network employing a four-quadrant multiplier
US4961002A (en) 1989-07-13 1990-10-02 Intel Corporation Synapse cell employing dual gate transistor structure
US4999525A (en) 1989-02-10 1991-03-12 Intel Corporation Exclusive-or cell for pattern matching employing floating gate devices
US5028810A (en) 1989-07-13 1991-07-02 Intel Corporation Four quadrant synapse cell employing single column summing line

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59175770A (ja) * 1983-03-25 1984-10-04 Toshiba Corp 半導体論理素子
JPS61255070A (ja) * 1985-05-08 1986-11-12 Seiko Epson Corp 半導体集積回路
US4951239A (en) * 1988-10-27 1990-08-21 The United States Of America As Represented By The Secretary Of The Navy Artificial neural network implementation
JP2823229B2 (ja) * 1989-04-05 1998-11-11 株式会社東芝 電子回路、差動増幅回路、及びアナログ乗算回路
JP2662559B2 (ja) * 1989-06-02 1997-10-15 直 柴田 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4950917A (en) 1988-07-27 1990-08-21 Intel Corporation Semiconductor cell for neural network employing a four-quadrant multiplier
US4999525A (en) 1989-02-10 1991-03-12 Intel Corporation Exclusive-or cell for pattern matching employing floating gate devices
US4961002A (en) 1989-07-13 1990-10-02 Intel Corporation Synapse cell employing dual gate transistor structure
US5028810A (en) 1989-07-13 1991-07-02 Intel Corporation Four quadrant synapse cell employing single column summing line

Also Published As

Publication number Publication date
WO1992016971A1 (fr) 1992-10-01
US5587668A (en) 1996-12-24
EP0578821B1 (en) 1999-07-07
TW208086B (cg-RX-API-DMAC7.html) 1993-06-21
DE69229546T2 (de) 2000-03-02
DE69229546D1 (de) 1999-08-12
TW203665B (cg-RX-API-DMAC7.html) 1993-04-11
EP0578821A1 (en) 1994-01-19
EP0578821A4 (en) 1996-01-10

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