FI981301A0 - Prosessivaihtelujen eliminointimenetelmä u-MOSFET-rakenteissa - Google Patents

Prosessivaihtelujen eliminointimenetelmä u-MOSFET-rakenteissa

Info

Publication number
FI981301A0
FI981301A0 FI981301A FI981301A FI981301A0 FI 981301 A0 FI981301 A0 FI 981301A0 FI 981301 A FI981301 A FI 981301A FI 981301 A FI981301 A FI 981301A FI 981301 A0 FI981301 A0 FI 981301A0
Authority
FI
Finland
Prior art keywords
process variations
eliminating process
mosfet structures
mosfet
structures
Prior art date
Application number
FI981301A
Other languages
English (en)
Swedish (sv)
Inventor
Arto Rantala
Original Assignee
Valtion Teknillinen
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Valtion Teknillinen filed Critical Valtion Teknillinen
Priority to FI981301A priority Critical patent/FI981301A0/fi
Publication of FI981301A0 publication Critical patent/FI981301A0/fi
Priority to PCT/FI1999/000494 priority patent/WO1999067827A2/fi
Priority to EP99931268A priority patent/EP1093669A2/en
Priority to AU47826/99A priority patent/AU4782699A/en
Priority to US09/719,133 priority patent/US6501126B1/en

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C27/00Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/005Electric analogue stores, e.g. for storing instantaneous values with non-volatile charge storage, e.g. on floating gate or MNOS
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/788Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881Programmable transistors with only two possible levels of programmation
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B69/00Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
FI981301A 1998-06-08 1998-06-08 Prosessivaihtelujen eliminointimenetelmä u-MOSFET-rakenteissa FI981301A0 (fi)

Priority Applications (5)

Application Number Priority Date Filing Date Title
FI981301A FI981301A0 (fi) 1998-06-08 1998-06-08 Prosessivaihtelujen eliminointimenetelmä u-MOSFET-rakenteissa
PCT/FI1999/000494 WO1999067827A2 (fi) 1998-06-08 1999-06-08 Semiconductor structure and procedure for minimising nonidealities
EP99931268A EP1093669A2 (en) 1998-06-08 1999-06-08 Semiconductor structure and procedure for minimising non-idealities
AU47826/99A AU4782699A (en) 1998-06-08 1999-06-08 Semiconductor structure and procedure for minimising non-idealities
US09/719,133 US6501126B1 (en) 1998-06-08 1999-06-08 Semiconductor structure and procedure for minimizing non-idealities

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FI981301A FI981301A0 (fi) 1998-06-08 1998-06-08 Prosessivaihtelujen eliminointimenetelmä u-MOSFET-rakenteissa

Publications (1)

Publication Number Publication Date
FI981301A0 true FI981301A0 (fi) 1998-06-08

Family

ID=8551931

Family Applications (1)

Application Number Title Priority Date Filing Date
FI981301A FI981301A0 (fi) 1998-06-08 1998-06-08 Prosessivaihtelujen eliminointimenetelmä u-MOSFET-rakenteissa

Country Status (5)

Country Link
US (1) US6501126B1 (fi)
EP (1) EP1093669A2 (fi)
AU (1) AU4782699A (fi)
FI (1) FI981301A0 (fi)
WO (1) WO1999067827A2 (fi)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4331968A (en) 1980-03-17 1982-05-25 Mostek Corporation Three layer floating gate memory transistor with erase gate over field oxide region
TW203665B (fi) * 1991-03-21 1993-04-11 Shibata Naoru
US5294819A (en) 1992-11-25 1994-03-15 Information Storage Devices Single-transistor cell EEPROM array for analog or digital storage
JP3337599B2 (ja) * 1995-07-24 2002-10-21 株式会社リコー 半導体装置およびインバータ回路並びにコンパレータ並びにa/dコンバータ回路
US6008508A (en) * 1996-09-12 1999-12-28 National Semiconductor Corporation ESD Input protection using a floating gate neuron MOSFET as a tunable trigger element
JP4330670B2 (ja) * 1997-06-06 2009-09-16 株式会社東芝 不揮発性半導体記憶装置

Also Published As

Publication number Publication date
EP1093669A2 (en) 2001-04-25
US6501126B1 (en) 2002-12-31
AU4782699A (en) 2000-01-10
WO1999067827A2 (fi) 1999-12-29
WO1999067827A3 (fi) 2000-02-10

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