JP2828950B2 - 半導体メモリ装置のパッド構造 - Google Patents

半導体メモリ装置のパッド構造

Info

Publication number
JP2828950B2
JP2828950B2 JP8085291A JP8529196A JP2828950B2 JP 2828950 B2 JP2828950 B2 JP 2828950B2 JP 8085291 A JP8085291 A JP 8085291A JP 8529196 A JP8529196 A JP 8529196A JP 2828950 B2 JP2828950 B2 JP 2828950B2
Authority
JP
Japan
Prior art keywords
pull
terminal
active
protection line
semiconductor memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP8085291A
Other languages
English (en)
Japanese (ja)
Other versions
JPH08316436A (ja
Inventor
香子 梁
煕哲 朴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sansei Denshi Co Ltd
Original Assignee
Sansei Denshi Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sansei Denshi Co Ltd filed Critical Sansei Denshi Co Ltd
Publication of JPH08316436A publication Critical patent/JPH08316436A/ja
Application granted granted Critical
Publication of JP2828950B2 publication Critical patent/JP2828950B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/998—Input and output buffer/driver structures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP8085291A 1995-04-06 1996-04-08 半導体メモリ装置のパッド構造 Expired - Lifetime JP2828950B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019950007970A KR0145476B1 (ko) 1995-04-06 1995-04-06 칩면적을 줄일 수 있는 패드구조를 가지는 반도체 메모리 장치
KR1995P7970 1995-04-06

Publications (2)

Publication Number Publication Date
JPH08316436A JPH08316436A (ja) 1996-11-29
JP2828950B2 true JP2828950B2 (ja) 1998-11-25

Family

ID=19411620

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8085291A Expired - Lifetime JP2828950B2 (ja) 1995-04-06 1996-04-08 半導体メモリ装置のパッド構造

Country Status (6)

Country Link
US (1) US5962899A (enExample)
JP (1) JP2828950B2 (enExample)
KR (1) KR0145476B1 (enExample)
FR (1) FR2732811B1 (enExample)
GB (1) GB2299705B (enExample)
TW (1) TW301050B (enExample)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6815775B2 (en) * 2001-02-02 2004-11-09 Industrial Technology Research Institute ESD protection design with turn-on restraining method and structures
KR100605195B1 (ko) * 2004-12-31 2006-07-31 동부일렉트로닉스 주식회사 정전 방전 보호 회로를 구비한 패드
US7755587B2 (en) 2005-06-30 2010-07-13 Seiko Epson Corporation Integrated circuit device and electronic instrument
JP4010335B2 (ja) 2005-06-30 2007-11-21 セイコーエプソン株式会社 集積回路装置及び電子機器
JP4661400B2 (ja) 2005-06-30 2011-03-30 セイコーエプソン株式会社 集積回路装置及び電子機器
KR100828792B1 (ko) 2005-06-30 2008-05-09 세이코 엡슨 가부시키가이샤 집적 회로 장치 및 전자 기기
US7764278B2 (en) 2005-06-30 2010-07-27 Seiko Epson Corporation Integrated circuit device and electronic instrument
JP4151688B2 (ja) 2005-06-30 2008-09-17 セイコーエプソン株式会社 集積回路装置及び電子機器
JP4830371B2 (ja) 2005-06-30 2011-12-07 セイコーエプソン株式会社 集積回路装置及び電子機器
JP4010336B2 (ja) 2005-06-30 2007-11-21 セイコーエプソン株式会社 集積回路装置及び電子機器
JP4186970B2 (ja) * 2005-06-30 2008-11-26 セイコーエプソン株式会社 集積回路装置及び電子機器
JP4010332B2 (ja) * 2005-06-30 2007-11-21 セイコーエプソン株式会社 集積回路装置及び電子機器
JP4665677B2 (ja) 2005-09-09 2011-04-06 セイコーエプソン株式会社 集積回路装置及び電子機器
JP4586739B2 (ja) 2006-02-10 2010-11-24 セイコーエプソン株式会社 半導体集積回路及び電子機器
JP4465343B2 (ja) 2006-12-05 2010-05-19 Ｏｋｉセミコンダクタ株式会社 半導体記憶装置
US8184414B2 (en) * 2008-07-30 2012-05-22 Qualcomm Incorporated Method and apparatus for forming I/O clusters in integrated circuits
US8218277B2 (en) * 2009-09-08 2012-07-10 Xilinx, Inc. Shared electrostatic discharge protection for integrated circuit output drivers

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4132904A (en) * 1977-07-28 1979-01-02 Hughes Aircraft Company Volatile/non-volatile logic latch circuit
JPS57211272A (en) * 1981-06-23 1982-12-25 Toshiba Corp Semiconductor device
JPS5943824B2 (ja) * 1982-03-03 1984-10-24 三菱電機株式会社 半導体集積回路装置
JPH061833B2 (ja) * 1982-11-11 1994-01-05 株式会社東芝 Ｍｏｓ形半導体装置
JPS60767A (ja) * 1983-06-17 1985-01-05 Hitachi Ltd 半導体装置
JP2538312B2 (ja) * 1988-06-02 1996-09-25 三菱電機株式会社 半導体集積回路
US5182621A (en) * 1988-06-14 1993-01-26 Nec Corporation Input protection circuit for analog/digital converting semiconductor
GB8921841D0 (en) * 1989-09-27 1989-11-08 Sarnoff David Res Center Nmos device with integral esd protection
JPH03273675A (ja) * 1990-03-23 1991-12-04 Matsushita Electron Corp 半導体装置
JP2953192B2 (ja) * 1991-05-29 1999-09-27 日本電気株式会社 半導体集積回路
JP2920013B2 (ja) * 1991-12-26 1999-07-19 川崎製鉄株式会社 半導体静電保護回路
JP2877175B2 (ja) * 1992-02-04 1999-03-31 日本電気株式会社 半導体入力保護装置
US5517048A (en) * 1993-07-23 1996-05-14 Vlsi Technology, Inc. Pad structure with parasitic MOS transistor for use with semiconductor devices

Also Published As

Publication number Publication date
JPH08316436A (ja) 1996-11-29
US5962899A (en) 1999-10-05
FR2732811A1 (fr) 1996-10-11
GB2299705B (en) 1997-08-13
KR0145476B1 (ko) 1998-08-17
KR960039231A (ko) 1996-11-21
GB9607365D0 (en) 1996-06-12
GB2299705A (en) 1996-10-09
FR2732811B1 (fr) 2000-04-07
TW301050B (enExample) 1997-03-21

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