JP2023526570A - 駆動回路の制御スイッチ、アレイ基板及び表示パネル - Google Patents
駆動回路の制御スイッチ、アレイ基板及び表示パネル Download PDFInfo
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Abstract
Description
Claims (20)
- 制御スイッチは薄膜トランジスタを含み、駆動回路は更に前記薄膜トランジスタに接続されたソースリード線を含み、前記薄膜トランジスタは、
少なくとも二つの並置されたソース分岐及び各ソース分岐を接続するソース幹部を含むソースと、
前記ソースと同層して設置され、少なくとも一つのドレイン分岐及び各前記ドレイン分岐を接続するドレイン幹部を含み、前記ドレイン分岐が前記ソース分岐と並列し且つ交互して設置されてチャネルドを形成するドレインと、
前記ソース、ドレインと対応して設置されたグリッドと、を含む駆動回路の制御スイッチであって、
前記ソースリード線に直接に接続された前記ソース分岐は第一ソース分岐であり、前記ソースリード線に直接に接続されない前記ソース分岐は第二ソース分岐であり、前記第一ソース分岐と隣接する前記ドレイン分岐との間のチャネルの幅は、前記第二ソース分岐と隣接する前記ドレイン分岐との間のチャネルの幅よりも大きい、駆動回路の制御スイッチ。 - 前記第一ソース分岐の数は二つであり、二つの前記第一ソース分岐はそれぞれ前記ソース幹部の両端に接続され、二つの前記ソースリード線はそれぞれ二つの前記第一ソース分岐に接続され、前記第二ソース分岐は二つの前記第一ソース分岐の間に並置され、前記ソース幹部に接続され、
前記ドレイン分岐において、前記ドレイン幹部の両端に接続されたのは第一ドレイン分岐と第二ドレイン分岐であり、前記第一ドレイン分岐は前記第一ソース分岐と前記第二ソース分岐との間に設置され、前記第二ドレイン分岐は他の前記第一ソース分岐と前記第二ソース分岐との間に設置される、請求項1に記載の駆動回路の制御スイッチ。 - 前記第二ソース分岐、前記第一ドレイン分岐及び前記第二ドレイン分岐の数はいずれも一つのみであり、前記ソースはW形構成であり、前記ドレインはU形構成である、請求項2に記載の駆動回路の制御スイッチ。
- 前記第一ドレイン分岐と前記第二ソース分岐との間のチャネルの幅は、前記第二ドレイン分岐と前記第二ソース分岐との間のチャネルの幅と同じであり、且つ前記第一ソース分岐と前記第一ドレイン分岐との間のチャネルの幅よりも小さく、前記第一ソース分岐と前記第二ドレイン分岐との間のチャネルの幅よりも小さい、請求項3に記載の駆動回路の制御スイッチ。
- 前記ソースは二つの第一ソース分岐と一つの前記ソース幹部だけがあり、前記ソースの形状はU型であり、前記ドレインは一つのみのドレイン分岐を有する、請求項1に記載の駆動回路の制御スイッチ。
- 前記第二ソース分岐の数は、少なくとも二つであり、前記ドレイン分岐において、前記ドレイン幹部の両端の間の領域に接続されたのは第三ドレイン分岐であり、前記第三ドレイン分岐は前記第一ドレイン分岐と前記第二ドレイン分岐との間に並置され、且つ前記第三ドレイン分岐は、隣接する二つの前記第二ソース分岐の間にも設置される、請求項2に記載の駆動回路の制御スイッチ。
- 前記ソースリード線は前記第一ソース分岐に垂直に接続され、且つ二つの前記ソースリード線は同じ直線に位置しない、請求項2に記載の駆動回路の制御スイッチ。
- 前記第一ソース分岐の数は一つであり、前記第一ソース分岐は前記ソース幹部の一端に接続され、一つの前記第二ソース分岐は前記ソース幹部の他端に接続され、
前記ドレイン分岐は前記第一ソース分岐と第二ソース分岐との間に設置される、請求項1に記載の駆動回路の制御スイッチ。 - 前記第二ソース分岐の数は少なくとも二つであり、前記ドレイン分岐において、前記ドレイン幹部の両端に接続されたのは第一ドレイン分岐と第二ドレイン分岐であり、前記ドレイン幹部の両端の間の領域に接続されたのは第三ドレイン分岐であり、
前記第一ドレイン分岐は隣接する前記第一ソース分岐と第二ソース分岐との間に並置され、前記第二ドレイン分岐と第三ドレイン分岐はそれぞれ隣接する二つの前記第二ソース分岐の間に並置される、請求項8に記載の駆動回路の制御スイッチ。 - 前記第一ソース分岐と隣接する前記ドレイン分岐との間のチャネルの幅は、前記第二ソース分岐と隣接する前記ドレイン分岐との間のチャネルの幅の1.1~1.2倍である、請求項1に記載の駆動回路の制御スイッチ。
- 前記第二ソース分岐と隣接する前記ドレイン分岐の間のチャネルの幅が3um~7umであり、前記第一ソース分岐と隣接する前記ドレイン分岐との間のチャネルの幅が3.1um~7.5umである、請求項10に記載の駆動回路の制御スイッチ。
- 前記ソース分岐と前記ドレイン分岐の形状はストリップ、矩形状又は長円形状である、請求項1に記載の駆動回路の制御スイッチ。
- 前記ソース分岐の延在方向は前記ソース幹部の延在方向と互いに垂直し、前記ドレイン分岐の延在方向は前記ドレイン幹部の延在方向と互いに垂直する、請求項1に記載の駆動回路の制御スイッチ。
- 前記ソース分岐の延在方向と前記ソース幹部の延在方向との間の夾角は鋭角であり、前記ドレイン分岐の延在方向と前記ドレイン幹部の延在方向との間の夾角は鋭角である、請求項1に記載の駆動回路の制御スイッチ。
- 前記ソース分岐、前記ソース幹部、前記ドレイン分岐及び前記ドレイン幹部の幅はいずれも同じである、請求項1に記載の駆動回路の制御スイッチ。
- 隣接する前記第二ソース分岐と前記ドレイン分岐との間のチャネルの幅は同じである、請求項1に記載の駆動回路の制御スイッチ。
- 駆動回路、ソースリード線及び前記駆動回路に駆動されるスキャンラインを含み、前記駆動回路の制御スイッチは、薄膜トランジスタを含み、前記薄膜トランジスタは前記ソースリード線に接続され、前記薄膜トランジスタは、ソース、ドレイン及びグリッドを含み、前記ソースは少なくとも二つの並置されたソース分岐及び各ソース分岐を接続するソース幹部を含み、前記ドレインは前記ソースと同層して設置され、少なくとも一つのドレイン分岐及び各前記ドレイン分岐を接続するドレイン幹部を含み、前記ドレイン分岐は前記ソース分岐と並列し、且つ交互して設置されてチャネルを形成し、前記グリッドは前記ソース、ドレインと対応して設置されたアレイ基板であって、前記ソースリード線に直接に接続された前記ソース分岐は第一ソース分岐であり、前記ソースリード線に直接に接続されない前記ソース分岐は第二ソース分岐であり、前記第一ソース分岐は隣接する前記ドレイン分岐との間のチャネルの幅は、前記第二ソース分岐と隣接する前記ドレイン分岐との間のチャネルの幅よりも大きい、アレイ基板。
- 前記駆動回路は、フレーム先頭信号線、ゲート電圧制御線、クロック信号線及び複数のグリッド駆動ユニットを含み、前記グリッド駆動ユニットの入力端子は前記フレーム先頭信号線、ゲート電圧制御線及びクロック信号線に接続され、前記スキャンラインを駆動させ、前記ゲート電圧制御線はソースリード線によってグリッド駆動ユニットにおける一つの薄膜トランジスタに接続される、請求項17に記載のアレイ基板。
- 前記グリッド駆動ユニットは、第一薄膜トランジスタ、第二薄膜トランジスタ、第三薄膜トランジスタ及び第四薄膜トランジスタを含み、前記第一薄膜トランジスタのソースはそれぞれ2本の前記ソースリード線によって前記ゲート電圧制御線、前記第二薄膜トランジスタのソースに接続され、前記第一薄膜トランジスタのドレインはそれぞれ前記第三薄膜トランジスタのソース、第四薄膜トランジスタのグリッドに接続され、前記第一薄膜トランジスタのグリッドは前記第二薄膜トランジスタのグリッドに接続され、前記第二薄膜トランジスタのドレインは前記第四薄膜トランジスタのソースに接続され、前記第二薄膜トランジスタのグリッドは前記第四薄膜トランジスタのグリッドに接続され、前記第三薄膜トランジスタのドレインは前記フレーム先頭信号線と連通され、前記第四薄膜トランジスタのドレインは前記クロック信号線と連通される、請求項18に記載のアレイ基板。
- アレイ基板、前記アレイ基板と対向して設置されたカラーフィルム基板、及び前記アレイ基板とカラーフィルム基板との間に設置された液晶層を含み、前記アレイ基板は駆動回路、ソースリード線及び前記駆動回路に駆動されたスキャンラインを含み、前記駆動回路の制御スイッチは、薄膜トランジスタを含み、前記薄膜トランジスタは前記ソースリード線に接続され、前記薄膜トランジスタはソース、ドレイン及びグリッドを含み、前記ソースは少なくとも二つの並置されたソース分岐、及び各ソース分岐を接続するソース幹部を含み、前記ドレインは前記ソースと同層して設置され、少なくとも一つのドレイン分岐及び各前記ドレイン分岐を接続するドレイン幹部を含み、前記ドレイン分岐は前記ソース分岐と並列し且つ交互して設置されてチャネルを形成し、前記グリッドは前記ソース、ドレインと対応して設置された表示パネルであって、前記ソースリード線に直接に接続された前記ソース分岐は第一ソース分岐であり、前記ソースリード線に直接に接続されない前記ソース分岐は第二ソース分岐であり、前記第一ソース分岐と隣接する前記ドレイン分岐との間のチャネルの幅は、前記第二ソース分岐と隣接する前記ドレイン分岐との間のチャネルの幅よりも大きい、表示パネル。
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