JP2020504451A5 - - Google Patents

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Publication number
JP2020504451A5
JP2020504451A5 JP2019536063A JP2019536063A JP2020504451A5 JP 2020504451 A5 JP2020504451 A5 JP 2020504451A5 JP 2019536063 A JP2019536063 A JP 2019536063A JP 2019536063 A JP2019536063 A JP 2019536063A JP 2020504451 A5 JP2020504451 A5 JP 2020504451A5
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JP
Japan
Prior art keywords
semiconductor device
packaged semiconductor
polymer
particles
packaged
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2019536063A
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English (en)
Japanese (ja)
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JP2020504451A (ja
JP7206198B2 (ja
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Publication date
Priority claimed from US15/842,608 external-priority patent/US10186478B2/en
Application filed filed Critical
Publication of JP2020504451A publication Critical patent/JP2020504451A/ja
Publication of JP2020504451A5 publication Critical patent/JP2020504451A5/ja
Application granted granted Critical
Publication of JP7206198B2 publication Critical patent/JP7206198B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2019536063A 2016-12-30 2017-12-28 表面が粗化された粒子を有するパッケージングされた半導体デバイス Active JP7206198B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201662440950P 2016-12-30 2016-12-30
US62/440,950 2016-12-30
US15/842,608 2017-12-14
US15/842,608 US10186478B2 (en) 2016-12-30 2017-12-14 Packaged semiconductor device with a particle roughened surface
PCT/US2017/068761 WO2018126038A1 (en) 2016-12-30 2017-12-28 Packaged semiconductor device with a particle roughened surface

Publications (3)

Publication Number Publication Date
JP2020504451A JP2020504451A (ja) 2020-02-06
JP2020504451A5 true JP2020504451A5 (https=) 2021-02-12
JP7206198B2 JP7206198B2 (ja) 2023-01-17

Family

ID=62710747

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019536063A Active JP7206198B2 (ja) 2016-12-30 2017-12-28 表面が粗化された粒子を有するパッケージングされた半導体デバイス

Country Status (4)

Country Link
US (3) US10186478B2 (https=)
JP (1) JP7206198B2 (https=)
CN (1) CN109863594B (https=)
WO (1) WO2018126038A1 (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10186478B2 (en) * 2016-12-30 2019-01-22 Texas Instruments Incorporated Packaged semiconductor device with a particle roughened surface
US12237249B2 (en) * 2018-10-30 2025-02-25 Texas Instruments Incorporated Substrates with solder barriers on leads
JP7353794B2 (ja) 2019-05-13 2023-10-02 ローム株式会社 半導体装置、その製造方法、及びモジュール
US11264314B2 (en) 2019-09-27 2022-03-01 International Business Machines Corporation Interconnection with side connection to substrate
US11004819B2 (en) * 2019-09-27 2021-05-11 International Business Machines Corporation Prevention of bridging between solder joints
WO2021065907A1 (ja) * 2019-10-03 2021-04-08 ローム株式会社 半導体装置、電子部品および電子部品の製造方法
JP7408885B2 (ja) * 2020-01-30 2024-01-09 長華科技股▲ふん▼有限公司 リードフレーム
US11235404B2 (en) * 2020-03-21 2022-02-01 International Business Machines Corporation Personalized copper block for selective solder removal
JP7607438B2 (ja) * 2020-11-13 2024-12-27 ローム株式会社 半導体装置
US11735529B2 (en) 2021-05-21 2023-08-22 International Business Machines Corporation Side pad anchored by next adjacent via
CN116995054B (zh) * 2023-07-13 2025-04-01 日月新半导体(昆山)有限公司 集成电路封装产品以及集成电路封装方法

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06204362A (ja) * 1993-01-05 1994-07-22 Nec Corp 半導体装置
JP2953424B2 (ja) * 1997-03-31 1999-09-27 日本電気株式会社 フェイスダウンボンディング用リードフレーム
JPH11289040A (ja) * 1998-02-09 1999-10-19 Shinko Electric Ind Co Ltd リードフレーム及びこれを用いた半導体装置
SG87769A1 (en) 1998-09-29 2002-04-16 Texas Instr Singapore Pte Ltd Direct attachment of semiconductor chip to organic substrate
JP4351327B2 (ja) 1999-05-20 2009-10-28 大日本印刷株式会社 リードフレーム部材とそれを用いた樹脂封止型半導体装置およびリードフレーム部材の製造方法
KR100583494B1 (ko) * 2000-03-25 2006-05-24 앰코 테크놀로지 코리아 주식회사 반도체패키지
JP2002170838A (ja) * 2000-11-30 2002-06-14 Shinkawa Ltd 半導体装置およびその製造方法
DE10148120B4 (de) * 2001-09-28 2007-02-01 Infineon Technologies Ag Elektronische Bauteile mit Halbleiterchips und ein Systemträger mit Bauteilpositionen sowie Verfahren zur Herstellung eines Systemträgers
US7645640B2 (en) * 2004-11-15 2010-01-12 Stats Chippac Ltd. Integrated circuit package system with leadframe substrate
US8067823B2 (en) * 2004-11-15 2011-11-29 Stats Chippac, Ltd. Chip scale package having flip chip interconnect on die paddle
US7443015B2 (en) * 2005-05-05 2008-10-28 Stats Chippac Ltd. Integrated circuit package system with downset lead
US7382059B2 (en) * 2005-11-18 2008-06-03 Semiconductor Components Industries, L.L.C. Semiconductor package structure and method of manufacture
JP5247626B2 (ja) * 2008-08-22 2013-07-24 住友化学株式会社 リードフレーム、樹脂パッケージ、半導体装置及び樹脂パッケージの製造方法
JP2010135723A (ja) 2008-10-29 2010-06-17 Panasonic Corp 半導体装置
JP5156658B2 (ja) 2009-01-30 2013-03-06 株式会社日立製作所 Lsi用電子部材
US8044495B2 (en) * 2009-06-22 2011-10-25 Texas Instruments Incorporated Metallic leadframes having laser-treated surfaces for improved adhesion to polymeric compounds
RU2438845C1 (ru) 2010-07-01 2012-01-10 Открытое акционерное общество "Авангард" Припойная паста
CN103563099A (zh) 2011-06-01 2014-02-05 皇家飞利浦有限公司 键合到支撑衬底的发光器件
CN102339809B (zh) * 2011-11-04 2013-11-06 北京工业大学 一种多圈引脚排列四边扁平无引脚封装及制造方法
JP5842109B2 (ja) 2012-02-23 2016-01-13 パナソニックIpマネジメント株式会社 樹脂封止型半導体装置及びその製造方法
US9040346B2 (en) * 2012-05-03 2015-05-26 Infineon Technologies Ag Semiconductor package and methods of formation thereof
TWI460837B (zh) 2012-06-19 2014-11-11 頎邦科技股份有限公司 半導體封裝結構及其導線架
CN104425287A (zh) 2013-08-19 2015-03-18 讯芯电子科技(中山)有限公司 封装结构及制造方法
US20160068387A1 (en) * 2014-09-09 2016-03-10 Texas Instruments Incorporated Semiconductor cavity package using photosensitive resin
US9502337B2 (en) 2014-10-31 2016-11-22 Nantong Fujitsu Microelectronics Co., Ltd. Flip-chip on leadframe semiconductor packaging structure and fabrication method thereof
US10008472B2 (en) * 2015-06-29 2018-06-26 Stmicroelectronics, Inc. Method for making semiconductor device with sidewall recess and related devices
US10186478B2 (en) * 2016-12-30 2019-01-22 Texas Instruments Incorporated Packaged semiconductor device with a particle roughened surface

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