TWI460837B - 半導體封裝結構及其導線架 - Google Patents

半導體封裝結構及其導線架 Download PDF

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TWI460837B
TWI460837B TW101121828A TW101121828A TWI460837B TW I460837 B TWI460837 B TW I460837B TW 101121828 A TW101121828 A TW 101121828A TW 101121828 A TW101121828 A TW 101121828A TW I460837 B TWI460837 B TW I460837B
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bonding
semiconductor package
package structure
bumps
height
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TW101121828A
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TW201401469A (zh
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Chih Ming Kuo
Shih Chieh Chang
Chih Hsien Ni
Chin Tang Hsieh
Chia Jung Tu
Lung Hua Ho
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Chipbond Technology Corp
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Priority to TW101121828A priority Critical patent/TWI460837B/zh
Priority to US13/613,309 priority patent/US8704345B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

半導體封裝結構及其導線架
本發明係有關於一種半導體封裝結構，特別係有關於一種不需助焊劑(flux)之半導體封裝結構。
習知半導體封裝結構係利用銲料電性連接導線架及晶片，且在回焊之步驟中必須添加助焊劑，然而在回焊之步驟中，若銲料過度坍塌則使得導線架及晶片之接合強度及電性可靠度降低，且回焊後還必須清除助焊劑，增加製程複雜度。
本發明之主要目的係在於提供一種半導體封裝結構，其包含一導線架、至少一晶片以及一封膠體，該導線架係具有複數個引腳，各該引腳係具有一第一端部、一連接該第一端部之半蝕刻部及至少一結合凸部，該第一端部係具有一第一上表面及一第一下表面，該半蝕刻部係具有一第二上表面及一第二下表面，該結合凸部係一體形成於該第一上表面且該結合凸部係具有一環牆，該晶片係設置於該些引腳上方，該晶片係具有複數個凸塊及複數個形成於該些凸塊之銲料，該些結合凸部係嵌入於該些銲料以使該些銲料包覆該些結合凸部之該些環牆，且該些銲料係覆蓋該些第一上表面，該封膠體係包覆該晶片及該些引腳，且該封膠體係顯露出各該第一端部之該第一下表面。由於該些結合凸部係一體形成於該些引腳，因此在熱壓合製程中，該些結合凸部可直接穿透 該些銲料並連接該晶片之該些凸塊，使得該導線架電性連接該晶片，因而提高該導線架及該晶片間之電性可靠度及結合強度，同時可省略助焊劑之使用及助焊劑之清除以降低製程複雜度，且可維持該些銲料之接合高度。
請參閱第1及2圖，其係本發明之一較佳實施例，一種半導體封裝結構100係包含一導線架110、至少一晶片120以及一封膠體130，請參閱第2圖，該導線架110係具有複數個引腳111，各該引腳111係具有一第一端部112、一連接該第一端部112之半蝕刻部113、一連接該半蝕刻部113之第二端部114及至少一結合凸部115，該半蝕刻部113係位於該第一端部112及該第二端部114之間，該第一端部112係具有一第一上表面112a及一第一下表面112b，該半蝕刻部113係具有一第二上表面113a及一第二下表面113b，該第二端部114係具有一第三上表面114a及一第三下表面114b，該結合凸部115係一體形成於該第一上表面112a且該結合凸部115係具有一環牆115a，各該環牆115a係為傾斜面，請再參閱第1圖，該晶片120係設置於該些引腳111上方，該晶片120係具有複數個凸塊121、複數個形成於該些凸塊121之銲料122及複數個導接墊123，該些凸塊121係結合於該晶片120的該些導接墊123，各該銲料122係具有一第一高度H1，各該凸塊121係具有一第二高度H2，該第二高度H2係不小於該第一高度H1，該些引腳111之該些結合凸部115係嵌入於該些銲料122以使該些銲料122包覆該些結合凸部115之該些環牆115a，且該些銲料122係覆蓋該些第一端 部112之該些第一上表面112a以增加該晶片120及該導線架110之結合強度並提高電性可靠度。
請再參閱第1圖，在本實施例中，該些結合凸部115係另具有複數個結合面115b，該些凸塊121係具有複數個頂面121a，各該結合凸部115之各該結合面115b係具有一第一寬度W1，各該頂面121a係具有一第二寬度W2，該第一寬度W1係不大於該第二寬度W2，且該些結合面115b係抵觸該些頂面121a，該封膠體130係包覆該晶片120及該些引腳111，且該封膠體130係顯露出各該第一端部112之該第一下表面112b及各該第二端部114之該第三下表面114b。
此外，請參閱第3圖，在另一實施例中，該導線架110係另具有一接合層116，該接合層116係形成於該些第一上表面112a、該些第一下表面112b、該些第二上表面113a、該些第二下表面113b、該些第三上表面114a及該些第三下表面114b以防止該導線架110之該些引腳111過度氧化，該接合層116之材質係為鎳/鈀/金。
本發明之目的係在熱壓合該晶片120及該導線架110的製程中，藉由一體形成於該些引腳111之該些結合凸部115直接穿透該些銲料122並連接該晶片120之該些凸塊121，使得該導線架110電性連接該晶片120，其係可省略助焊劑之使用及助焊劑之清除以降低製程複雜度，此外，由於該些結合凸部115係具有該些結合面115b及固定之高度，因此在熱壓合製程中可維持該些銲料122之接合高度且藉由該些結合面115b抵觸該些凸塊121之該些頂面121a，提高該導線架110及該晶片120間之電性可靠度及 結合強度。
本發明之保護範圍當視後附之申請專利範圍所界定者為準，任何熟知此項技藝者，在不脫離本發明之精神和範圍內所作之任何變化與修改，均屬於本發明之保護範圍。
100‧‧‧半導體封裝結構
110‧‧‧導線架
111‧‧‧引腳
112‧‧‧第一端部
112a‧‧‧第一上表面
112b‧‧‧第一下表面
113‧‧‧半蝕刻部
113a‧‧‧第二上表面
113b‧‧‧第二下表面
114‧‧‧第二端部
114a‧‧‧第三上表面
114b‧‧‧第三下表面
115‧‧‧結合凸部
115a‧‧‧環牆
115b‧‧‧結合面
116‧‧‧接合層
120‧‧‧晶片
121‧‧‧凸塊
121a‧‧‧頂面
122‧‧‧銲料
123‧‧‧導接墊
130‧‧‧封膠體
H1‧‧‧第一高度
H2‧‧‧第二高度
W1‧‧‧第一寬度
W2‧‧‧第二寬度
第1圖：依據本發明之一較佳實施例，一種半導體封裝結構之截面示意圖。
第2圖：依據本發明之一較佳實施例，該半導體封裝結構中導線架之局部示意圖。
第3圖：依據本發明之另一實施例，一種半導體封裝結構之截面示意圖。
100‧‧‧半導體封裝結構
110‧‧‧導線架
111‧‧‧引腳
112‧‧‧第一端部
112a‧‧‧第一上表面
112b‧‧‧第一下表面
113‧‧‧半蝕刻部
113a‧‧‧第二上表面
113b‧‧‧第二下表面
114‧‧‧第二端部
114a‧‧‧第三上表面
114b‧‧‧第三下表面
115‧‧‧結合凸部
115a‧‧‧環牆
115b‧‧‧結合面
120‧‧‧晶片
121‧‧‧凸塊
121a‧‧‧頂面
122‧‧‧銲料
123‧‧‧導接墊
130‧‧‧封膠體
H1‧‧‧第一高度
H2‧‧‧第二高度
W1‧‧‧第一寬度
W2‧‧‧第二寬度

Claims (7)

  1. 一種半導體封裝結構，其至少包含：一導線架，其係具有複數個引腳，各該引腳係具有一第一端部、一連接該第一端部之半蝕刻部及至少一結合凸部，該第一端部係具有一第一上表面及一第一下表面，該半蝕刻部係具有一第二上表面及一第二下表面，該結合凸部係一體形成於該第一上表面且該結合凸部係具有一環牆；至少一晶片，其係設置於該些引腳上方，該晶片係具有複數個凸塊及複數個形成於該些凸塊之銲料，該些結合凸部係嵌入於該些銲料以使該些銲料包覆該些結合凸部之該些環牆，且該些銲料係覆蓋該些第一上表面；以及一封膠體，其係包覆該晶片及該些引腳，且該封膠體係顯露出各該第一端部之該第一下表面。
  2. 如申請專利範圍第1項所述之半導體封裝結構，其中該些結合凸部係另具有複數個結合面，該些凸塊係具有複數個頂面，各該結合面係具有一第一寬度，各該頂面係具有一第二寬度，該第一寬度係不大於該第二寬度。
  3. 如申請專利範圍第2項所述之半導體封裝結構，其中該些結合面係抵觸該些頂面。
  4. 如申請專利範圍第1項所述之半導體封裝結構，其中各該引腳係另具有一連接該半蝕刻部之第二端部，該半蝕刻部係位於該第一端部及該第二端部之間，該第二端部係具有一第三上表面及一第三下表面且該封膠體係顯露各該第三下表面。
  5. 如申請專利範圍第1項所述之半導體封裝結構，其中該導 線架係另具有一接合層，該接合層係形成於該些第一上表面、該些第一下表面、該些第二上表面及該些第二下表面。
  6. 如申請專利範圍第1項所述之半導體封裝結構，其中各該銲料係具有一第一高度，各該凸塊係另具有一第二高度，該第二高度係不小於該第一高度。
  7. 如申請專利範圍第1項所述之半導體封裝結構，其中各該環牆係為傾斜面。
TW101121828A 2012-06-19 2012-06-19 半導體封裝結構及其導線架 TWI460837B (zh)

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US13/613,309 US8704345B2 (en) 2012-06-19 2012-09-13 Semiconductor package and lead frame thereof

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US20200135627A1 (en) * 2018-10-30 2020-04-30 Texas Instruments Incorporated Substrates with solder barriers on leads

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US20130334671A1 (en) 2013-12-19

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