JP2020145468A - ピクセル型温度制御式基板支持アセンブリ - Google Patents
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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Abstract
Description
本明細書に記載した実施形態は、一般的に、半導体製造に関し、特に、温度制御式基板支持アセンブリ及びそれを用いる方法に関する。
デバイスパターンの加工寸法が小さくなると、これらの加工の臨界寸法(CD)要件は、安定しかつ繰り返し可能なデバイス性能のさらに重要な判断基準になる。処理チャンバ内において処理される基板全体の許容可能なCDのばらつきは、チャンバ及び基板温度等のチャンバ非対称性、フローコンダクタンス、ならびにRFフィールドにより、達成するのが困難である。
(実施例1)
チャンバ本体と、
上面及び下面を含むピクセル型基板支持アセンブリと、
ピクセル型基板支持アセンブリ内に配置された1つ又は複数の主抵抗ヒータと、
主抵抗ヒータと列をなし、またピクセル型基板支持体内に配置される複数のピクセルヒータと、を含む処理チャンバであって、ピクセルヒータの数量は、主抵抗ヒータの数量より1桁大きく、ピクセルヒータは、主抵抗ヒータと同様に、互いに対して独立して制御可能である処理チャンバ。
(実施例2)
ピクセル型基板支持体は、静電チャックである実施例1の処理チャンバ。
(実施例3)
静電チャックが、セラミック本体を有する実施例1の処理チャンバ。
(実施例4)
主抵抗ヒータ及び複数のピクセルヒータの内の少なくとも1つが、セラミック本体の下面に形成される実施例3の処理チャンバ。
(実施例5)
主抵抗ヒータ及び複数のピクセルヒータの内の少なくとも1つが、セラミック本体の下面に結合されたポリマ本体内に配置される実施例3の処理チャンバ。
(実施例6)
ピクセル型基板支持体に結合された冷却板をさらに含む実施例1の処理チャンバ。
(実施例7)
各ピクセルヒータの温度出力を調整するためのピクセルヒータ・コントローラが、冷却板に結合されている実施例6の処理チャンバ。
(実施例8)
ピクセルヒータ・コントローラには、光ファイバ制御回路及び電力制御手段が含まれる実施例7の処理チャンバ。
(実施例9)
基板支持面及び下面を有する基板支持体と、
基板支持体全体に配置された複数の抵抗ヒータであって、同心ゾーンにグループ化された複数の抵抗ヒータと、
各グループの抵抗ヒータに結合されたピクセルヒータ・コントローラであって、所定ゾーン内のどの抵抗ヒータが、その所定ゾーン内の他の抵抗ヒータより多くの熱を生成するかを制御するように動作可能なピクセルヒータ・コントローラとを含む基板支持アセンブリ。
(実施例10)
ピクセルヒータ・コントローラは、光ファイバ制御回路及び電力制御手段を含む実施例9の処理チャンバ。
(実施例11)
ピクセルヒータ・コントローラは、1つ又は複数のハードウェア配線キーを含む実施例9の処理チャンバ。
Claims (20)
- ピクセル型基板支持アセンブリであって、
上面及び下面を有するピクセル化基板支持体と、
ピクセル化基板支持体に配置された1つ以上の主抵抗ヒータと、
1つ以上の主抵抗ヒータと列をなし、ピクセル化基板支持体に配置された複数のピクセルヒータとを備え、
複数のピクセルヒータの数量は、1つ以上の主抵抗ヒータの数量よりも一桁大きく、
複数のピクセルヒータのうちのピクセルヒータの各組み合わせは、1つ以上の主抵抗ヒータの各々と同様に、複数のピクセルヒータのうちの他のすべてのピクセルヒータのオン状態を変更することなく、オン状態とオフ状態を独立して制御可能になっているピクセル型基板支持アセンブリ。 - ピクセル化基板支持体に結合された冷却板をさらに備える、請求項1に記載のピクセル型基板支持アセンブリ。
- 複数のピクセルヒータの各ピクセルヒータの温度出力を調整するように構成されたピクセルヒータコントローラであって、冷却板に結合されたピクセルヒータコントローラをさらに備える、請求項2に記載のピクセル型基板支持アセンブリ。
- 複数のピクセルヒータは、ピクセル化基板支持体の中心の周りに同心状に配置され、共通の半径に沿ってピクセルヒータのグループへ分けられている、請求項1に記載のピクセル型基板支持アセンブリ。
- 複数のピクセルヒータは、さらに極格子状に配置されている、請求項2に記載のピクセル型基板支持アセンブリ。
- 複数のピクセルヒータと上面との間に配置されたチャック電極をさらに備える、請求項1に記載のピクセル型基板支持アセンブリ。
- 複数のスイッチであって、各スイッチは、ピクセルヒータのそれぞれと独自に対になって、ピクセルヒータのそれぞれを、他の全てのピクセルヒータのオン状態に対して独立して制御している複数のスイッチをさらに備える、請求項1に記載のピクセル型基板支持アセンブリ。
- 基板支持アセンブリであって、
基板支持面と下面とを有する基板支持体と、
誘電体に結合又は配置された主抵抗ヒータと、
基板支持体に結合又は配置された複数の抵抗ヒータとを備え、
複数の抵抗ヒータのうちの各抵抗ヒータは、独立して対処可能であり、主抵抗ヒータと同様に、他の全ての抵抗ヒータのオン状態に対してオフ状態とオン状態を制御され、
抵抗ヒータの各組み合わせは、他の抵抗ヒータの各々に印加される電圧又は電流とは無関係に電圧又は電流を受け取るように構成されている基板支持アセンブリ。 - 複数の抵抗ヒータに接続されたヒータコントローラをさらに備え、
ヒータコントローラは、光学コントローラと電力コントローラとを含み、
光学コントローラは、複数の抵抗ヒータのうちの各抵抗ヒータのそれぞれのスイッチに光学的に接続され、
ヒータコントローラは、複数の抵抗ヒータのそれぞれに電力を供給するように構成されている、請求項8に記載の基板支持アセンブリ。 - 基板支持体に結合された冷却板をさらに備える、請求項8に記載の基板支持アセンブリ。
- 複数の抵抗ヒータと基板支持面との間に配置されたチャック電極をさらに備える、請求項8に記載の基板支持アセンブリ。
- 基板支持体は静電チャックであり、静電チャックの誘電体がセラミックである、請求項8に記載の基板支持アセンブリ。
- 複数の抵抗ヒータは、共通の半径に沿った抵抗ヒータのグループで同心状に配置されている、請求項8に記載の基板支持アセンブリ。
- 主抵抗ヒータは誘電体の下面に形成されている、請求項8に記載の基板支持アセンブリ。
- 主抵抗ヒータは、誘電体の下面に結合されたポリマ体内に配置されている、請求項8に記載の基板支持アセンブリ。
- 基板支持体に結合された冷却板をさらに備える、請求項8に記載の基板支持アセンブリ。
- 処理チャンバであって、
チャンバ本体と、
チャンバ本体内に配置されたピクセル型基板支持アセンブリであって、
上面及び下面を有するピクセル化基板支持体と、
ピクセル型基板支持アセンブリに配置された1つ以上の主抵抗ヒータとを備えるピクセル型基板支持アセンブリと、
1つ以上の主抵抗ヒータと列をなし、ピクセル化基板支持体に配置された複数のピクセルヒータとを備え、
複数のピクセルヒータの数量は、1つ以上の主抵抗ヒータの数量よりも一桁大きく、
複数のピクセルヒータのうちのピクセルヒータの各組み合わせは、1つ以上の主抵抗ヒータと同様に、複数のピクセルヒータのうちの他のすべてのピクセルヒータのオン状態を変更することなく、オン状態とオフ状態を独立して制御可能であり、
前記数量は2以上である、処理チャンバ。 - ピクセル化基板支持体は、セラミック体を有する静電チャックである、請求項17に記載の処理チャンバ。
- 主抵抗ヒータ及び複数のピクセルヒータの少なくとも一方は、セラミック体の下面に結合されたポリマ体に配置されている、請求項17に記載の処理チャンバ。
- 冷却板に結合され、複数のピクセルヒータの各ピクセルヒータの温度出力を調整するヒータコントローラをさらに備え、
ヒータコントローラは、ある範囲の電流又は電圧を各ピクセルヒータに供給し、
ヒータコントローラは、光ファイバ制御回路及び電力制御手段とを備えている、請求項17に記載の処理チャンバ。
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US201461937348P | 2014-02-07 | 2014-02-07 | |
US61/937,348 | 2014-02-07 | ||
US14/285,606 US11158526B2 (en) | 2014-02-07 | 2014-05-22 | Temperature controlled substrate support assembly |
US14/285,606 | 2014-05-22 |
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