JP2019102811A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2019102811A5 JP2019102811A5 JP2018221947A JP2018221947A JP2019102811A5 JP 2019102811 A5 JP2019102811 A5 JP 2019102811A5 JP 2018221947 A JP2018221947 A JP 2018221947A JP 2018221947 A JP2018221947 A JP 2018221947A JP 2019102811 A5 JP2019102811 A5 JP 2019102811A5
- Authority
- JP
- Japan
- Prior art keywords
- bit line
- memory cells
- integer
- line pair
- cell array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2017229785 | 2017-11-30 | ||
| JP2017229785 | 2017-11-30 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2019102811A JP2019102811A (ja) | 2019-06-24 |
| JP2019102811A5 true JP2019102811A5 (enExample) | 2022-01-06 |
| JP7337496B2 JP7337496B2 (ja) | 2023-09-04 |
Family
ID=66665461
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2018221947A Active JP7337496B2 (ja) | 2017-11-30 | 2018-11-28 | 記憶装置 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US11270997B2 (enExample) |
| JP (1) | JP7337496B2 (enExample) |
| KR (1) | KR102602338B1 (enExample) |
| CN (1) | CN111357053B (enExample) |
| TW (1) | TWI758567B (enExample) |
| WO (1) | WO2019106479A1 (enExample) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9153699B2 (en) * | 2012-06-15 | 2015-10-06 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor with multiple oxide semiconductor layers |
| WO2019162802A1 (ja) * | 2018-02-23 | 2019-08-29 | 株式会社半導体エネルギー研究所 | 記憶装置およびその動作方法 |
| WO2020074999A1 (ja) | 2018-10-12 | 2020-04-16 | 株式会社半導体エネルギー研究所 | 半導体装置、および半導体装置の作製方法 |
| CN113474897A (zh) | 2019-03-12 | 2021-10-01 | 株式会社半导体能源研究所 | 半导体装置及半导体装置的制造方法 |
| CN113632230B (zh) * | 2020-03-09 | 2024-03-05 | 铠侠股份有限公司 | 半导体存储装置及半导体存储装置的制造方法 |
| DE102020127961B4 (de) * | 2020-05-28 | 2025-08-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Speicherschaltung und schreibverfahren |
| US11450377B2 (en) * | 2020-07-29 | 2022-09-20 | Micron Technology, Inc. | Apparatuses and methods including memory cells, digit lines, and sense amplifiers |
| US11393822B1 (en) * | 2021-05-21 | 2022-07-19 | Micron Technology, Inc. | Thin film transistor deck selection in a memory device |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2761644B2 (ja) | 1989-03-16 | 1998-06-04 | 三菱電機株式会社 | 半導体記憶装置 |
| US5276649A (en) * | 1989-03-16 | 1994-01-04 | Mitsubishi Denki Kabushiki Kaisha | Dynamic-type semiconductor memory device having staggered activation of column groups |
| JPH03238862A (ja) * | 1990-02-15 | 1991-10-24 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JPH0494569A (ja) | 1990-08-10 | 1992-03-26 | Matsushita Electric Ind Co Ltd | 半導体集積回路装置 |
| US6188598B1 (en) | 1999-09-28 | 2001-02-13 | Infineon Technologies North America Corp. | Reducing impact of coupling noise |
| US6327169B1 (en) * | 2000-10-31 | 2001-12-04 | Lsi Logic Corporation | Multiple bit line memory architecture |
| US6430076B1 (en) | 2001-09-26 | 2002-08-06 | Infineon Technologies Ag | Multi-level signal lines with vertical twists |
| JP2003242773A (ja) * | 2002-02-14 | 2003-08-29 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
| JP2006128471A (ja) * | 2004-10-29 | 2006-05-18 | Toshiba Corp | 半導体メモリ |
| US20070058468A1 (en) | 2005-09-12 | 2007-03-15 | Promos Technologies Pte.Ltd. Singapore | Shielded bitline architecture for dynamic random access memory (DRAM) arrays |
| KR101820776B1 (ko) | 2010-02-19 | 2018-01-22 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 |
| WO2012002186A1 (en) | 2010-07-02 | 2012-01-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| KR20130029464A (ko) * | 2011-09-15 | 2013-03-25 | 윤재만 | 반도체 메모리 장치 |
| WO2013049920A1 (en) | 2011-10-04 | 2013-04-11 | Mosaid Technologies Incorporated | Reduced noise dram sensing |
| JP6105266B2 (ja) | 2011-12-15 | 2017-03-29 | 株式会社半導体エネルギー研究所 | 記憶装置 |
| TWI767772B (zh) * | 2014-04-10 | 2022-06-11 | 日商半導體能源研究所股份有限公司 | 記憶體裝置及半導體裝置 |
-
2018
- 2018-11-19 CN CN201880074987.8A patent/CN111357053B/zh active Active
- 2018-11-19 WO PCT/IB2018/059084 patent/WO2019106479A1/en not_active Ceased
- 2018-11-19 KR KR1020207016081A patent/KR102602338B1/ko active Active
- 2018-11-19 US US16/757,025 patent/US11270997B2/en active Active
- 2018-11-23 TW TW107141949A patent/TWI758567B/zh not_active IP Right Cessation
- 2018-11-28 JP JP2018221947A patent/JP7337496B2/ja active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2019102811A5 (enExample) | ||
| CN111771280A (zh) | 一种三维非易失性铁电存储器 | |
| JP2015228492A5 (ja) | 記憶装置 | |
| JP2016197484A5 (ja) | 送信装置 | |
| JP2012256837A5 (ja) | 半導体装置 | |
| SG10201806761YA (en) | Cell bottom node reset in a memory array | |
| RU2016107386A (ru) | Различные матрицы полых ячеек для подошвы | |
| JP2011181908A5 (enExample) | ||
| JP2014042029A5 (enExample) | ||
| JP2012256816A5 (enExample) | ||
| JP2018182320A5 (enExample) | ||
| JP2012084862A5 (enExample) | ||
| JP2015181159A5 (enExample) | ||
| RU2016106676A (ru) | Полупроводниковое запоминающее устройство | |
| JP2011129893A5 (enExample) | ||
| JP2010267373A5 (enExample) | ||
| JP2012113809A5 (ja) | フラッシュメモリ装置のメモリセルを読み出す方法 | |
| JP2012009701A5 (enExample) | ||
| JP2015130329A5 (ja) | 蓄電装置及び電子機器 | |
| JP2013178522A5 (ja) | 半導体装置 | |
| WO2008102650A1 (ja) | 半導体記憶装置 | |
| JP2017069420A5 (enExample) | ||
| JP2012028000A5 (enExample) | ||
| JP2014017029A5 (enExample) | ||
| JP2015213408A5 (enExample) |