JP2019062160A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2019062160A JP2019062160A JP2017187744A JP2017187744A JP2019062160A JP 2019062160 A JP2019062160 A JP 2019062160A JP 2017187744 A JP2017187744 A JP 2017187744A JP 2017187744 A JP2017187744 A JP 2017187744A JP 2019062160 A JP2019062160 A JP 2019062160A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 216
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- 238000009413 insulation Methods 0.000 abstract 2
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- 229910052782 aluminium Inorganic materials 0.000 description 11
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Abstract
Description
A−1.半導体装置の構成
図1は、第1実施形態における半導体装置100の構成を模式的に示す断面図である。本実施形態では、半導体装置100は、縦型トレンチMOSFET(Metal-Oxide-Semiconductor Field-Effect Transistor)である。本実施形態では、半導体装置100は、電力制御に用いられ、パワーデバイスとも呼ばれる。
以上説明したように、本実施形態の半導体装置100によれば、導電体146に加えて外周電極148を備えるため、アクティブ領域の最外周に位置する外周トレンチ129の底面端部近傍の電界集中を緩和できる。以下、半導体装置100により得られる効果について説明する。
図8は、第2実施形態における半導体装置100bの構成を模式的に示す断面図である。図8及びそれ以降の図では、理解を容易にする観点から、第1の絶縁膜130、第2の絶縁膜132、第3の絶縁膜150及び配線電極160の記載が省略されている。半導体装置100bは、第1実施形態における半導体装置100と比較して、最外周のトレンチ122とゲート電極142の形状が異なる。
図9は、第3実施形態における半導体装置100cの構成を模式的に示す断面図である。半導体装置100cは、第1実施形態における半導体装置100と比較して、導電体146の形状が異なる。
図10は、第4実施形態における半導体装置100dの構成を模式的に示す断面図である。半導体装置100dは、第1実施形態における半導体装置100と比較して、最も外周側のソース電極141の形状が異なる。
図11は、第5実施形態における半導体装置100eの構成を模式的に示す断面図である。半導体装置100eは、第1実施形態における半導体装置100と比較して、トレンチ122の外周の形状と、最も外周側のソース電極141e及び最も外周側のボディ電極144eの形状とが異なる。
本発明は、上述の実施形態や実施例に限られるものではなく、その趣旨を逸脱しない範囲において種々の構成で実現することができる。例えば、発明の概要の欄に記載した各形態中の技術的特徴に対応する実施形態、実施例、変形例中の技術的特徴は、上述の課題の一部または全部を解決するために、あるいは、上述の効果の一部または全部を達成するために、適宜、差し替えや、組み合わせを行うことが可能である。また、その技術的特徴が本明細書中に必須なものとして説明されていなければ、適宜、削除することが可能である。
100b…半導体装置
100c…半導体装置
100d…半導体装置
100e…半導体装置
110…基板
112…第1の半導体層
114…第2の半導体層
116…第3の半導体層
122…トレンチ
124…コンタクトホール
126…コンタクトホール
128…トレンチ
129…外周トレンチ
130…第1の絶縁膜
132…第2の絶縁膜
141…ソース電極
141d…接続部
141e…ソース電極
142…ゲート電極
142b…突出部
143…ドレイン電極
144…ボディ電極
144e…ボディ電極
146…導電体
146c…突出部
148…外周電極
150…第3の絶縁膜
160…配線電極
T1…領域
T2…領域
a…距離
b…距離
Claims (6)
- アクティブ領域と、前記アクティブ領域の外周を囲む非アクティブ領域と、を備える半導体装置であって、
第1導電型を有し、面方向に広がる第1の半導体層と、
前記第1の半導体層の上に形成され、前記第1導電型とは異なる第2導電型を有する第2の半導体層と、
前記第2の半導体層の上に形成され、前記第1導電型を有する第3の半導体層と、を備え、
前記第1の半導体層と、前記第2の半導体層と、前記第3の半導体層とは、ワイドバンドギャップ半導体により形成されており、
前記アクティブ領域は、
前記第3の半導体層と前記第2の半導体層とを貫通し、前記第1の半導体層まで到達したトレンチと、
前記トレンチの表面を覆う第1の絶縁膜と、
前記第1の絶縁膜に覆われた前記トレンチに形成された制御電極と、
前記第3の半導体層と接するコンタクト電極と、を備え、
前記非アクティブ領域は、
前記第3の半導体層と前記第2の半導体層とを貫通し、前記第1の半導体層まで到達しており、前記アクティブ領域を囲む外周トレンチと、
前記外周トレンチの表面を覆う第2の絶縁膜と、
前記第2の絶縁膜に覆われた前記外周トレンチに形成され、前記制御電極及び前記コンタクト電極と電気的に絶縁された導電体と、
前記外周トレンチの外側に位置し、前記第2の半導体層と接し、前記コンタクト電極と電気的に接続された外周電極と、を備える、半導体装置。 - 請求項1に記載の半導体装置であって、
前記第2の絶縁膜の誘電率は、前記第1の絶縁膜の誘電率よりも大きい、半導体装置。 - 請求項1または請求項2に記載の半導体装置であって、
前記面方向に直交する厚み方向から見たとき、
前記制御電極は、多角形を隙間無く並べた網目状の形状となっており、前記多角形の角のうち、最も前記導電体に近い角において、前記導電体に向かって突出する突出部を備える、半導体装置。 - 請求項1から請求項3のいずれか1項に記載の半導体装置であって、
前記面方向に直交する厚み方向から見たとき、
前記制御電極は、多角形を隙間無く並べた網目状の形状となっており、
前記導電体は、前記多角形を隙間無く並べた形状の外周に沿った形状となっており、
前記導電体は、前記導電体の前記多角形の角のうち、最も前記制御電極に近い角において、前記制御電極に向かって突出する突出部を備える、半導体装置。 - 請求項1から請求項4のいずれか1項に記載の半導体装置であって、
前記コンタクト電極を複数備え、
前記制御電極よりも外周側に配置され、前記導電体よりも内側に配置された複数の前記コンタクト電極において、隣接する前記コンタクト電極を電気的に接続する接続部を備える、半導体装置。 - 請求項1または請求項2に記載の半導体装置であって、
前記トレンチの最も外周側の端部は、前記外周トレンチまでの距離が一定となるように形成されている、半導体装置。
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