JP2018526831A5 - - Google Patents

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Publication number
JP2018526831A5
JP2018526831A5 JP2018512130A JP2018512130A JP2018526831A5 JP 2018526831 A5 JP2018526831 A5 JP 2018526831A5 JP 2018512130 A JP2018512130 A JP 2018512130A JP 2018512130 A JP2018512130 A JP 2018512130A JP 2018526831 A5 JP2018526831 A5 JP 2018526831A5
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JP
Japan
Prior art keywords
pmos transistor
sige
cavity
gate
source
Prior art date
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Application number
JP2018512130A
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English (en)
Japanese (ja)
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JP6948099B2 (ja
JP2018526831A (ja
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Priority claimed from US14/845,112 external-priority patent/US10026837B2/en
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Publication of JP2018526831A publication Critical patent/JP2018526831A/ja
Publication of JP2018526831A5 publication Critical patent/JP2018526831A5/ja
Application granted granted Critical
Publication of JP6948099B2 publication Critical patent/JP6948099B2/ja
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JP2018512130A 2015-09-03 2016-09-06 マルチ閾値PMOSトランジスタのための埋め込みSiGeプロセス Active JP6948099B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/845,112 US10026837B2 (en) 2015-09-03 2015-09-03 Embedded SiGe process for multi-threshold PMOS transistors
US14/845,112 2015-09-03
PCT/US2016/050409 WO2017041098A1 (en) 2015-09-03 2016-09-06 Embedded sige process for multi-threshold pmos transistors

Publications (3)

Publication Number Publication Date
JP2018526831A JP2018526831A (ja) 2018-09-13
JP2018526831A5 true JP2018526831A5 (https=) 2019-10-03
JP6948099B2 JP6948099B2 (ja) 2021-10-13

Family

ID=58188618

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018512130A Active JP6948099B2 (ja) 2015-09-03 2016-09-06 マルチ閾値PMOSトランジスタのための埋め込みSiGeプロセス

Country Status (5)

Country Link
US (2) US10026837B2 (https=)
EP (1) EP3345219B1 (https=)
JP (1) JP6948099B2 (https=)
CN (1) CN107924915B (https=)
WO (1) WO2017041098A1 (https=)

Families Citing this family (4)

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Publication number Priority date Publication date Assignee Title
KR101776926B1 (ko) * 2010-09-07 2017-09-08 삼성전자주식회사 반도체 소자 및 그 제조 방법
CN110970487B (zh) * 2018-09-28 2023-12-19 台湾积体电路制造股份有限公司 半导体器件及其形成方法
US11315838B2 (en) 2018-09-28 2022-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET device and method of forming same
US12349454B2 (en) * 2022-02-17 2025-07-01 Taiwan Semiconductor Manufacturing Company, Ltd. Checkerboard dummy design for epitaxial open ratio

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