CN107924915B - 用于多阈值PMOS晶体管的嵌入式SiGe工艺 - Google Patents

用于多阈值PMOS晶体管的嵌入式SiGe工艺 Download PDF

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CN107924915B
CN107924915B CN201680043865.3A CN201680043865A CN107924915B CN 107924915 B CN107924915 B CN 107924915B CN 201680043865 A CN201680043865 A CN 201680043865A CN 107924915 B CN107924915 B CN 107924915B
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Y·崔
D·J·瑞里
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Texas Instruments Inc
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Abstract

在所描述的具有第一PMOS晶体管(205)和第二PMOS晶体管(215)的集成电路和方法的示例中，第一PMOS晶体管(205)具有延伸区(210)和袋区注入物(212)并且具有SiGe源极和漏极(230)，第二PMOS晶体管(215)不具有延伸区且不具有袋区注入物而具有SiGe源极和漏极(230)，第一PMOS晶体管(205)的从SiGe源极和漏极(230)到栅极的距离(C2Gd)比第二PMOS晶体管(215)的从SiGe源极和漏极(230)到栅极的距离(C2Gu)大，并且第一PMOS晶体管(205)的导通电压比第二PMOS晶体管(215)的导通电压高至少50mV。

Description

用于多阈值PMOS晶体管的嵌入式SiGe工艺
技术领域
本发明总体涉及集成电路，并且更特别地涉及具有硅锗源极和漏极扩散的PMOS晶体管。
背景技术
嵌入SiGe源极/漏极区的技术已经被用于CMOS器件以增加PMOS器件沟道区中的压应力，从而通过提高空穴迁移率来提高器件性能。在这样的工艺流程中，在形成栅极叠层和源极/漏极延伸区之后，在PMOS器件的源极/漏极区中形成空腔。通常通过多步干法刻蚀工艺以及随后的湿法刻蚀工艺来完成空腔形成。
第一干法刻蚀步骤是第一各向异性干法刻蚀，该步骤被用于蚀穿所沉积的硬掩模层(例如，氮化硅)以开始在衬底(例如，硅)中刻蚀空腔，接着进行扩大空腔的各向同性干法横向刻蚀(干法横向刻蚀)(包括横向朝向PMOS晶体管沟道扩大空腔)，接着进行第二各向异性干法刻蚀以限定空腔的底壁。
一般先进行多步干法刻蚀，接着进行湿法结晶刻蚀，这样形成“菱形的”空腔。用于结晶刻蚀的湿法刻蚀剂对衬底材料有晶向选择性，例如包含四甲基氢氧化铵(TMAH)的刻蚀剂，该刻蚀剂被用于从由多步干法刻蚀处理提供的U形凹槽开始刻蚀衬底。在湿法结晶刻蚀工艺中，<111>晶向的刻蚀速度小于其他晶向(如<100>)的刻蚀速度。结果，U形凹槽变成菱形凹槽。
图1A是示出正好在形成SiGe(硅锗)源极和漏极扩散区之前的处理中的PMOS晶体管的示意图。所示的PMOS晶体管具有包括在衬底102(例如硅)上的栅电极104的栅极叠层，以及在栅极叠层壁上的侧壁隔离物116和在栅电极104上的硬掩模层(例如，氮化硅)106。P型源极和漏极延伸区110以及n型晕圈(halo)或袋区112被形成为与偏移的隔离物108电介质(例如二氧化硅或氮化硅)自对准。p型延伸区110将PMOS晶体管沟道电连接到形成触点的深源极漏极。n型袋区112增加PMOS晶体管沟道114中的掺杂并且设置PMOS晶体管导通电压(vtp)。
图1B示出正好在完成多步干法空腔刻蚀处理之后的PMOS晶体管。典型地，第一干法刻蚀步骤是第一各向异性干法刻蚀，该步骤被用于蚀穿所沉积的硬掩模层(例如，氮化硅)并且开始将空腔刻蚀到衬底102中。接着进行各向同性干法横向刻蚀步骤，该步骤朝向PMOS晶体管沟道114横向扩展空腔118。该刻蚀一般接下来进行第二各向异性干法刻蚀以限定空腔120的底壁。
图1C示出湿法结晶空腔刻蚀形成菱形的凹槽122之后的处理中的PMOS晶体管的示意图。C2G(空腔至栅极间隙)是从空腔的边缘到晶体管栅极的边缘的距离。
在湿法结晶刻蚀之后，硼掺杂的SiGe在菱形凹槽中外延生长以形成嵌入了SiGe源极/漏极区的PMOS。嵌入的SiGe区与PMOS晶体管沟道的外边缘间隔足够近，从而它们对通道施加大量的压应力。然而，SiGe区不过于接近PMOS晶体管沟道的外边缘，以使掺杂物从SiGe中的原位掺杂扩散进入PMOS沟道并改变PMOS阈值电压(vtp)。
除了核心PMOS晶体管之外，集成电路经常要求具有低导通电压的PMOS晶体管(LVPMOS)用于高性能电路。典型地，一种图案化和注入步骤被用来设置核心PMOS晶体管的vt，并且第二种图案化和注入步骤被用来设置LVPMOS晶体管的较低vtp。
发明内容
在所描述的示例中，形成具有第一PMOS晶体管和第二PMOS晶体管的集成电路，第一PMOS晶体管具有延伸区和袋区注入物并具有SiGe源极和漏极，第二PMOS晶体管不具有延伸区且不具有袋区注入物而具有SiGe源极和漏极。第一PMOS晶体管的从SiGe源极和漏极到栅极的距离大于第二PMOS晶体管的从SiGe源极和漏极到栅极的距离。第一PMOS晶体管的导通电压高于第二PMOS晶体管的导通电压。所描述的示例包括形成具有第一PMOS晶体管和第二PMOS晶体管的集成电路的方法，第一PMOS晶体管具有延伸区和袋区注入物并具有SiGe源极和漏极，第二PMOS晶体管不具有延伸区且不具有袋区注入物而具有SiGe源极和漏极。第一PMOS晶体管的从SiGe源极和漏极到栅极的距离大于第二PMOS晶体管的从SiGe源极和漏极到栅极的距离，并且第一PMOS晶体管的导通电压高于第二PMOS晶体管的导通电压。
附图说明
图1A-1C(现有技术)是在PMOS晶体管上形成SiGe源极和漏极的横截面。
图2A至图2E是集成电路的横截面，其中以连续制造阶段描述低电压PMOS晶体管的实施例。
具体实施方式
这些图不是按比例绘制的，并且它们仅仅被提供用于图示说明示例实施例。以下参考用于图示说明的示例应用来描述几个方面。为了便于理解，阐述了许多具体的细节、关系和方法。然而，相关领域的技术人员将容易认识到这些实施例可以在没有一个或多个具体细节或利用其他方法的情况下实践。在其他实例中，熟知的结构或操作未被详细示出以避免混淆。一些动作与其他的动作或事件可能以不同的顺序和/或同时发生。此外，实施一种方法并非需要所有图示说明的动作或事件。
为了本说明书的目的，术语“C2Gd”是指具有延伸区和袋区掺杂的PMOS晶体管的SiGe空腔到栅极间隙。术语“C2Gu”是指不具有延伸区和袋区掺杂(无掺杂)的LVPMOS晶体管的SiGe空腔到栅极间隙。
图2E示出了根据一些实施例形成的集成电路的一部分，该集成电路包括具有SiGe源极和漏极的核心PMOS晶体管205和具有SiGe源极和漏极的低电压PMOS(LVPMOS)晶体管215。形成具有较低vtp的LVPMOS晶体管215不需要额外的光刻或注入步骤。核心PMOS晶体管205具有源极和漏极延伸区210和袋区212。LVPMOS晶体管215不具有源极和漏极延伸区并且不具有袋区。另外，在核心PMOS晶体管上的SiGe空腔到栅极间隙(C2Gd)大于LVPMOS晶体管的SiGe空腔到栅极间隙(C2Gu)。在LVPMOS晶体管上袋区掺杂的缺失和较小的SiGe空腔到栅极间隙导致晶体管具有较低的导通电压。LVPMOS晶体管上的较小的空腔SiGe到栅极间隙也使得LVPMOS晶体管的源极和漏极扩散区电连接到晶体管沟道而不增加串联电阻。
在图2A至2E所描述的集成电路制造流程中逐步说明一种方法，该方法仅使用一种延伸图案化和注入步骤来形成具有SiGe源极和漏极扩散区的核心PMOS晶体管和具有SiGe源极和漏极扩散区的LVPMOS晶体管。
图2A示出穿过集成电路中的PMOS晶体管栅极204的横截面。具有电介质覆盖层206的PMOS晶体管栅极204被形成在n型衬底202上。n型衬底可以是在p型衬底中形成的n阱。浅沟槽隔离结构(STI)218使核心PMOS晶体管205与LVPMOS晶体管215电隔离。在集成电路上形成核心PMOS延伸光刻胶图案224，该图案阻止延伸区注入物226和袋区注入物228进入LVPMOS晶体管215，并且使核心PMOS晶体管205对延伸区注入物226和袋区注入物228是开放的。p型延伸注入物226可以自对准到偏移隔离物208(例如SiO2或Si3N4的电介质)以形成核心PMOS源极和漏极延伸区210。可以注入与偏移隔离物208自对准的n型晕圈或袋区注入物228以调节核心PMOS晶体管沟道114的掺杂，从而设置导通电压(vtp)。在执行延伸和晕圈注入之后，光刻胶图案224被去除。
图2B示出在PMOS晶体管栅极204上形成SiGe隔离物侧壁216之后的集成电路。SiGe隔离物侧壁216和电介质覆盖层206完全包围栅极204以阻止在栅极204材料上外延生长SiGe。在示例实施例中，SiGe隔离物侧壁是大约20nm的氮化硅。
图2C示出多步干法刻蚀在衬底202中形成U形空腔220A(用于核心PMOS晶体管205)和U形空腔220B(用于LVPMOS晶体管215)之后的集成电路。例如，第一干法刻蚀步骤可以是第一各向异性干法刻蚀，该步骤被用于蚀穿所沉积的硬掩模层(例如，氮化硅)并且开始将空腔220A和空腔220B刻蚀到衬底202中。接着进行各向同性干法横向刻蚀步骤，该步骤朝向沟道横向扩展空腔。在该刻蚀之后接着进行第二各向异性干法刻蚀以限定空腔220A和空腔220B的底壁。此时，U形空腔220A和U形空腔220B两者都类似地与隔离物216对准。
如图2D所示，使用湿法结晶刻蚀沿着衬底202中的结晶平面刻蚀以产生“菱形”空腔222A和“菱形”空腔222B。用于结晶刻蚀的湿法刻蚀剂对衬底材料有晶向选择性，例如包含四甲基氢氧化铵(TMAH)的刻蚀剂，该刻蚀剂被用于从由多步干法刻蚀处理提供的U形凹槽220A和U形凹槽220B(图2C)开始刻蚀衬底。在湿法结晶刻蚀工艺中，<111>晶向的刻蚀速度小于其他晶向(如<100>)的刻蚀速度。结果，U形凹槽220A和U形凹槽220B变成菱形。
因为硼掺杂延缓了湿法结晶刻蚀，所以正在形成LVPMOS 215晶体管的轻掺杂硅(没有延伸区和袋区注入物)比通过延伸注入物226而更重掺杂的PMOS晶体管205的硅刻蚀得更快。结果，空腔220B在隔离物216下面比空腔220A在空腔的表面/顶部延伸得更远。在侧壁216的厚度大约为20nm和硼扩展区掺杂为1.2×1014/cm2的示例性实施例中，在LVPMOS晶体管215上具有轻掺杂衬底时空腔到栅极间隙(C2Gu)大约是5nm，相比之下，在核心PMOS晶体管205上具有硼掺杂延伸区时空腔到栅极间隙(C2Gd)为15nm。LVPMOS晶体管上的较小C2Gu使p型SiGe连接到LVPMOS晶体管215沟道而不需要延伸注入物。而且，因为SiGe将会更靠近LVPMOS晶体管215上的晶体管沟道，所以应力会增加，另外改善了LVPMOS晶体管的性能。SiGe更靠近晶体管沟道以及缺少袋区注入物的组合降低了LVPMOS晶体管的导通电压。在示例实施例中，LVPMOS晶体管215的导通电压比核心PMOS晶体管205的导通电压低大约200mV。
现在参考图2E，p型掺杂SiGe 230被外延生长以分别填充核心PMOS 205晶体管上的菱形空腔222A和LVPMOS 215晶体管上的菱形空腔222B。p型掺杂SiGe与LVPMOS晶体管的沟道足够近(C2Gu)以将p型SiGe电连接到LVPMOS晶体管215的沟道而不需要p型延伸注入物，而p型掺杂SiGe离核心PMOS晶体管的沟道太远(C2Gd)而不能形成电连接。然后可以执行额外的处理以添加深源极和漏极扩散区、硅化物、触点和互连层以完成集成电路。
如果需要的话，可以以低能量注入掺杂物以在注入n阱掺杂物时微调LVPMOS晶体管215的导通电压。
仅使用一个延伸区和袋区图案化和注入步骤来同时形成具有SiGe源极和漏极的核心PMOS晶体管205和具有SiGe源极和漏极的LVPMOS晶体管215。与传统方法相比，这节省了显著的成本和周期时间，该传统方法对于核心PMOS205晶体管和LVPMOS 215晶体管要求单独的图案化和注入步骤。
在所描述的实施例中修改是可能的，并且在权利要求的范围内的其他实施例是可能的。

Claims (16)

1.一种集成电路，其包括：
第一PMOS晶体管，其具有源极和漏极延伸区并具有袋区，所述第一PMOS晶体管包含具有第一SiGe空腔至栅极距离的SiGe源极和漏极；以及
第二PMOS晶体管，其不具有源极和漏极延伸区且不具有袋区，所述第二PMOS晶体管包含具有第二SiGe空腔至栅极距离的SiGe源极和漏极；
其中，由于所述第一PMOS晶体管中的所述源极和漏极延伸区和袋区以及所述第二PMOS晶体管中没有源极和漏极延伸区和袋区，因此通过使用湿法结晶刻蚀形成所述第一SiGe空腔的刻蚀速度小于通过使用所述湿法结晶刻蚀形成所述第二SiGe空腔的刻蚀速度，从而所述第二SiGe空腔至栅极距离小于所述第一SiGe空腔至栅极距离，使得所述第二PMOS晶体管的导通电压低于所述第一PMOS晶体管的导通电压。
2.根据权利要求1所述的集成电路，其中所述第二PMOS晶体管的导通电压比所述第一PMOS晶体管的导通电压低至少50mV。
3.根据权利要求1所述的集成电路，其中所述第二PMOS晶体管的导通电压比所述第一PMOS晶体管的导通电压低大约200mV。
4.根据权利要求1所述的集成电路，其中所述第一SiGe空腔至栅极距离是所述第二SiGe空腔至栅极距离的大约三倍。
5.根据权利要求1所述的集成电路，进一步包括在所述第一PMOS晶体管的栅极上的SiGe隔离物侧壁和在所述第二PMOS晶体管的栅极上的SiGe隔离物侧壁，其中所述SiGe隔离物侧壁的厚度是大约20nm，并且其中所述第一SiGe空腔至栅极距离是大约15nm，并且其中所述第二SiGe空腔至栅极距离是大约5nm。
6.一种形成集成电路的工艺，其包括：
形成第一PMOS晶体管的第一PMOS晶体管栅极，所述第一PMOS晶体管具有与所述第一PMOS晶体管栅极自对准的源极和漏极延伸区注入物和袋区注入物；
形成第二PMOS晶体管的第二PMOS晶体管栅极，所述第二PMOS晶体管不具有源极和漏极延伸区注入物且不具有袋区注入物；
在所述第一PMOS晶体管栅极和所述第二PMOS晶体管栅极上形成SiGe隔离物侧壁；
在所述第一PMOS晶体管的源极和漏极区中干法刻蚀与所述SiGe隔离物侧壁自对准的第一U形空腔，并且在所述第二PMOS晶体管的源极和漏极区中干法刻蚀与所述SiGe隔离物侧壁自对准的第二U形空腔；以及
使用湿法结晶刻蚀将所述第一U形空腔和所述第二U形空腔分别转换为第一菱形空腔和第二菱形空腔，其中，由于所述第二PMOS晶体管中没有源极和漏极延伸区和袋区，因此通过使用所述湿法结晶刻蚀形成所述第一菱形空腔的刻蚀速度小于通过使用所述湿法结晶刻蚀形成所述第二菱形空腔的刻蚀速度，从而从所述第一菱形空腔到所述第一PMOS晶体管的栅极的距离大于从所述第二菱形空腔到所述第二PMOS晶体管的栅极的距离，使得所述第一PMOS晶体管的导通电压比所述第二PMOS晶体管的导通电压高至少50mV。
7.根据权利要求6所述的工艺，其中所述第一PMOS晶体管的导通电压比所述第二PMOS晶体管的导通电压高大约200mV。
8.根据权利要求6所述的工艺，其中所述SiGe隔离物侧壁的厚度是大约20nm。
9.根据权利要求6所述的工艺，其中所述SiGe隔离物侧壁的厚度是大约20nm，并且其中从所述第一菱形空腔到所述第一PMOS晶体管的栅极的距离是大约15nm，并且其中从所述第二菱形空腔到所述第二PMOS晶体管的栅极的距离是大约5nm。
10.根据权利要求6所述的工艺，其中所述湿法结晶刻蚀使用四甲基氢氧化铵。
11.一种形成集成电路的工艺，其包括：
形成第一PMOS晶体管的第一PMOS栅极和第二PMOS晶体管的第二PMOS栅极；
形成光刻胶图案，所述光刻胶图案暴露所述第一PMOS晶体管的区域并覆盖所述第二PMOS晶体管的区域；
利用所述光刻胶图案，在所述第一PMOS晶体管中注入源极和漏极延伸区，而在所述第二PMOS晶体管中不注入源极和漏极延伸区；
利用所述光刻胶图案，在所述第一PMOS晶体管中注入袋区，而不将袋区注入到所述第二PMOS晶体管内；
去除所述光刻胶图案；
在所述第一PMOS栅极和所述第二PMOS栅极上形成SiGe隔离物侧壁；以及
在所述第二PMOS晶体管中不形成源极和漏极延伸区的情况下，在所述第一PMOS晶体管中形成第一SiGe空腔并且在所述第二PMOS晶体管中形成第二SiGe空腔，其中，由于所述第二PMOS晶体管中没有源极和漏极延伸区和袋区，因此通过使用湿法结晶刻蚀形成所述第一SiGe空腔的刻蚀速度小于通过使用所述湿法结晶刻蚀形成所述第二SiGe空腔的刻蚀速度，从而所述第一PMOS晶体管的第一SiGe空腔至栅极间隙大于所述第二PMOS晶体管的第二SiGe空腔至栅极间隙，使得所述第一PMOS晶体管的导通电压比所述第二PMOS晶体管的导通电压高至少50mV。
12.根据权利要求11所述的工艺，其中所述第一PMOS晶体管的导通电压比所述第二PMOS晶体管的导通电压高大约200mV。
13.根据权利要求11所述的工艺，其中所述SiGe隔离物侧壁的厚度是大约20nm。
14.根据权利要求11所述的工艺，其中所述SiGe隔离物侧壁的厚度是大约20nm，并且其中所述第一SiGe空腔至栅极间隙是大约15nm，并且其中所述第二SiGe空腔至栅极间隙是大约5nm。
15.根据权利要求11所述的工艺，其中所述第一SiGe空腔和所述第二SiGe空腔是菱形的并且由以下工艺形成：
在所述第一PMOS晶体管的源极和漏极区中干法刻蚀与所述SiGe隔离物侧壁自对准的第一U形空腔，并且在所述第二PMOS晶体管的源极和漏极区中干法刻蚀与所述SiGe隔离物侧壁自对准的第二U形空腔；以及
执行湿法结晶刻蚀以将所述第一U形空腔和所述第二U形空腔分别转换为第一菱形空腔和第二菱形空腔，其中所述湿法结晶刻蚀在表面处横向刻蚀所述第二U形空腔比横向刻蚀所述第一U形空腔更快，以形成比所述第二PMOS晶体管的所述第二SiGe空腔至栅极间隙更大的所述第一PMOS晶体管的所述第一SiGe空腔至栅极间隙。
16.根据权利要求15所示的工艺，其中所述湿法结晶刻蚀使用四甲基氢氧化铵。
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