JP2018509761A - 共平面型酸化物半導体tft基板構造及びその製作方法 - Google Patents
共平面型酸化物半導体tft基板構造及びその製作方法 Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 77
- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 claims abstract description 85
- 229910052751 metal Inorganic materials 0.000 claims abstract description 74
- 239000002184 metal Substances 0.000 claims abstract description 74
- 230000008569 process Effects 0.000 claims abstract description 48
- 238000002161 passivation Methods 0.000 claims description 39
- 238000001259 photo etching Methods 0.000 claims description 37
- 239000000463 material Substances 0.000 claims description 35
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 16
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052782 aluminium Inorganic materials 0.000 claims description 16
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 16
- 229910052802 copper Inorganic materials 0.000 claims description 16
- 239000010949 copper Substances 0.000 claims description 16
- 229910052750 molybdenum Inorganic materials 0.000 claims description 16
- 239000011733 molybdenum Substances 0.000 claims description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 16
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 12
- 229910044991 metal oxide Inorganic materials 0.000 claims description 10
- 150000004706 metal oxides Chemical group 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 10
- 238000005516 engineering process Methods 0.000 description 5
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical group [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052725 zinc Inorganic materials 0.000 description 2
- 239000011701 zinc Substances 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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Abstract
Description
100 基板
210 第一ゲート電極
220 第二ゲート電極
300 ゲート絶縁層
310 第一スルーホール
410 ソース電極
420 ドレイン電極
425 第二スルーホール
500 活性層
510 チャンネル
520 本体
600 パッシベーション層
610 第三スルーホール
(本発明)
10 基板
21 第一ゲート電極
22 第二ゲート電極
30 ゲート絶縁層
31 第一スルーホール
41 ソース電極
42 ドレイン電極
43 金属ストリップ電極
50 活性層
51 本体
52 チャンネル
60 パッシベーション層
61 第三スルーホール
421 第二スルーホール
Claims (11)
- 基板と、基板に配置された第一ゲート電極及び第二ゲート電極と、第一ゲート及び第二ゲート及び基板に配置されたゲート絶縁層と、ゲート絶縁層に配置されたソース電極及びドレイン電極と、ソース電極とドレイン電極の間に間隔を開けて設けられた数本の金属ストリップ電極と、前記ソース電極及びドレイン電極及び金属ストリップ電極及びゲート絶縁層に配置された活性層と、前記活性層及びソース電極及びドレイン電極に配置されたパッシベーション層と、からなる共平面型酸化物半導体TFT基板構造であって、
その内、前記活性層は、本体と、本体を連接されるとともにソース電極及びドレイン電極の間に配置された数本の短チャネルとからなり、前記数本の短チャネルは、数本の金属ストリップ電極によって間を仕切られている
ことを特徴とする、共平面型酸化物半導体TFT基板構造。 - 前記ゲート絶縁層における前記第二ゲート電極に対応する上方に第一スルーホールが設けられ、前記ドレイン電極は第一スルーホールによって第二ゲート電極と連接される
ことを特徴とする、請求項1に記載の共平面型酸化物半導体TFT基板構造。 - 前記ドレイン電極には第二スルーホールを設け、前記パッシベーション層は第二スルーホールで填充され、
その内、前記パッシベーション層における前記ドレイン電極に対応する上方に第三スルーホールが設けられる
ことを特徴とする、請求項1に記載の共平面型酸化物半導体TFT基板構造。 - 前記活性層の材料は金属酸化物であり、
前記第一ゲート電極及び第二ゲート電極の材料は銅、アルミ、もしくはモリブデンであり、
前記ゲート絶縁層の材料は酸化シリコンもしくは窒化ケイ素である
ことを特徴とする、請求項1に記載の共平面型酸化物半導体TFT基板構造。 - 前記ソース電極、ドレイン電極及び金属ストリップ電極の材料は、銅、アルミ、もしくはモリブデンであり、
前記パッシベーション層の材料は窒化ケイ素もしくは酸化シリコンである
ことを特徴とする請求項1に記載の共平面型酸化物半導体TFT基板構造。 - 共平面型酸化物半導体TFT基板構造の製作方法であって
前記製作方法は、
基板を提供し、基板に第一金属層を沈積させるとともにフォトエッチングプロセスによって第一金属層をパターン化させ、間隔を開けて設けられる第一ゲート電極と第二ゲート電極を形成させる手順1と、
前記第一ゲート電極と、第二ゲート電極と、基板にゲート絶縁層を沈積させるとともに、フォトエッチングプロセスによってそれをパターン化させ、前記ゲート絶縁層における前記第二ゲート電極に対応する上方に第一スルーホールを形成させる手順2と、
前記ゲート絶縁層に第二金属層を沈積させ、フォトエッチングプロセスによって第二金属層をパターン化させ、ソース電極及びドレイン電極と、ソース電極及びドレイン電極の間に間隔を開けて設けられた数本の金属ストリップ電極を形成させ、その内、前記ドレイン電極は第一スルーホールによって第二ゲート電極と連接され、前記ドレイン電極に第二スルーホールを形成させる手順3と、
前記ソース電極と、ドレイン電極と、金属ストリップ電極と、ゲート絶縁層とに酸化物半導体層を沈積させるとともに、フォトエッチングプロセスによってそれをパターン化し、活性層を形成させ、その内、前記活性層は、本体と、本体に連接されるとともにソース電極及びドレイン電極の間に設けられた数本の短チャネルとからなり、前記数本の短チャネルは数本の金属ストリップ電極によって間が仕切られる手順4と、
前記活性層と、ソース電極及びドレイン電極にパッシベーション層を沈積させるとともに、フォトエッチングプロセスによってそれをパターン化させ、前記パッシベーション層におけるドレイン電極に対応する上方に第三スルーホールを形成させ、前記パッシベーション層は前記ドレイン電極の第二スルーホールで填充されている手順5と、からなる
ことを特徴とする、共平面型酸化物半導体TFT基板構造の製作方法。 - 前記活性層の材料は金属酸化物である
ことを特徴とする、請求項6に記載の共平面型酸化物半導体TFT基板構造の製作方法。 - 前記第一ゲート電極及び第二ゲート電極の材料は銅、アルミ、もしくはモリブデンであり、
その内前記ゲート絶縁層の材料は酸化シリコンもしくは窒化ケイ素である
ことを特徴とする、請求項6に記載の共平面型酸化物半導体TFT基板構造の製作方法。 - 前記ソース電極、ドレイン電極及び金属ストリップ電極の材料は銅、アルミ、もしくはモリブデンである
ことを特徴とする、請求項6に記載の共平面型酸化物半導体TFT基板構造の製作方法。 - 前記パッシベーション層の材料は窒化ケイ素もしくは酸化シリコンである
ことを特徴とする、請求項6に記載の共平面型酸化物半導体TFT基板構造の製作方法。 - 共平面型酸化物半導体TFT基板構造の製作方法であって、
前記製作方法は、
基板を提供し、基板に第一金属層を沈積させるとともにフォトエッチングプロセスによって第一金属層をパターン化し、間隔を開けて設けられる第一ゲート電極と第二ゲート電極を形成させる手順1と、
前記第一ゲート電極と、第二ゲート電極と、基板にゲート絶縁層を沈積させるとともに、フォトエッチングプロセスによってそれをパターン化させ、前記ゲート絶縁層における前記第二ゲート電極に対応する上方に第一スルーホールを形成させる手順2と、
前記ゲート絶縁層に第二金属層を沈積させるとともに、フォトエッチングプロセスによって第二金属層をパターン化させ、ソース電極及びドレイン電極と、ソース電極及びドレイン電極の間に間隔を開けて設けられた数本の金属ストリップ電極を形成させ、その内、前記ドレイン電極は第一スルーホールによって第二ゲート電極と連接され、前記ドレイン電極には第二スルーホールが形成される手順3と、
前記ソース電極と、ドレイン電極と、金属ストリップ電極と、ゲート絶縁層とに酸化物半導体層を沈積させるとともに、フォトエッチングプロセスによってそれをパターン化し、活性層を形成させ、その内、前記活性層は、本体と、本体に連接されるとともにソース電極及びドレイン電極の間に設けられた数本の短チャネルとからなり、前記数本の短チャネルは数本の金属ストリップ電極によって間が仕切られる手順4と、
前記活性層と、ソース電極及びドレイン電極にパッシベーション層を沈積させるとともに、フォトエッチングプロセスによってそれをパターン化させ、前記パッシベーション層におけるドレイン電極に対応する上方に第三スルーホールを形成させ、前記パッシベーション層は前記ドレイン電極の第二スルーホールで填充され、その内、前記活性層の材料は金属酸化物であり、前記第一ゲート電極及び第二ゲート電極の材料は銅、アルミ、もしくはモリブデンであり、前記ゲート絶縁層の材料は酸化シリコンもしくは窒化ケイ素であり、その内、前記ソース電極及びドレイン電極、及び金属ストリップ電極の材料は銅、アルミ、もしくはモリブデンであり、前記パッシベーション層の材料は窒化ケイ素もしくは酸化シリコンである手順5と、からなる
ことを特徴とする、共平面型酸化物半導体TFT基板構造の製作方法。
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PCT/CN2015/081729 WO2016179877A1 (zh) | 2015-05-11 | 2015-06-18 | 共平面型氧化物半导体tft基板结构及其制作方法 |
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